Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-03-29

2003-09-02

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S205000, C365S207000

Reexamination Certificate

active

06614679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device including a dynamic random access memory (DRAM). In particular, the present invention relates to a technique for increasing the speed of the DRAM.
2. Description of the Related Art
The following is an explanation of a “low latency DRAM cell” such as that disclosed in U.S. Pat. No. 5,856,940. The low latency DRAM cell employs a dual word line and dual bit line system, in which each memory cell (2T/1C memory cell) includes two transistors (2T) and a storage capacitor (1C) and is connected to two word lines and two bit lines.
FIG. 1
is a diagram showing the circuit structure of a memory cell used in a conventional semiconductor memory device including the low latency DRAM cells. In
FIG. 1
, a memory cell
100
includes a first switching transistor
102
, a second switching transistor
103
, and a storage capacitor
104
.
The first switching transistor
102
has a gate connected to a first word line WL
0
A, a drain connected to a first bit line BL
0
A, and a source connected to a storage node
101
. The second switching transistor
103
has a gate connected to a second word line WL
0
B, a drain connected to a second bit line BL
0
B, and a source connected to the storage node
101
. The storage capacitor
104
has two electrodes: one is connected to the storage node
101
and the other acts as a cell plate (CP).
As described above, the memory cell
100
includes the first and second switching transistors
102
,
103
, which can be controlled independently with respect to the storage capacitor
104
. Therefore, it is possible to interleave the first word line WL
0
A and the first bit line BL
0
A with the second word line WL
0
B and the second bit line BL
0
B in a plurality of memory cells
100
, thereby enabling high-speed reading and writing operations.
The minimum random cycle time for memory cell
100
is defined as a period of time needed to perform reading and writing operations reliably. For the reading operation, charge that has been stored in the storage capacitor
104
is rewritten by a sense amplifier (not shown), so that the operation is completed at high speed. For the writing operation, however, when data that is opposite logically to the charge stored in the storage capacitor
104
is written, the time required for charging becomes longer. Thus, the writing operation takes more time to be completed than the reading operation, which in turn increases the random access cycle time. This is a problem in providing a high-speed DRAM.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor memory device that can reduce the time required for completion of a writing operation on a 2T/1C or 1T/1C memory cell so as to speed up a random access cycle.
To achieve the above object, a semiconductor memory device according to the present invention includes the following: a memory cell for retaining data by storing charge in a storage capacitor; a bit line that is connected selectively to the memory cell by activation of a word line; a sense amplifier connected to the bit line; and a sense amplifier driving circuit for generating a driving signal to drive the sense amplifier. The sense amplifier driving circuit activates the driving signal with timing that differs in writing and reading, and write data is transferred to the bit line before activating the driving signal in writing.
In this semiconductor memory device, it is preferable that the sense amplifier driving circuit generates the driving signal at an earlier time for writing than for reading.
According to the above configuration, the sense amplifier starts amplification early in writing as compared with reading. Therefore, the bit line has a sufficient voltage for writing in the early stages, so that a sufficient charge can be transferred to the storage capacitor in a short time. This makes it possible to reduce the time required for writing and to increase the operating speed of the semiconductor memory device.
It is preferable that the semiconductor memory device of the present invention further includes a sense amplifier starting signal generation circuit for generating a sense amplifier starting signal at an earlier time for writing than for reading, and the sense amplifier driving circuit operates in response to the sense amplifier starting signal.
This configuration makes it possible to implement the present invention by only adjusting the timing in the sense amplifier starting signal generation circuit.
In the semiconductor memory device of the present invention, it is preferable that the sense amplifier driving circuit includes a transistor that activates the driving signal in accordance with a decode signal only in writing.
This configuration enables precise control that changes timing for starting amplification by the sense amplifier in accordance with the decode signal.
In the semiconductor memory device of the present invention, it is preferable that the sense amplifier driving circuit generates the driving signal before a selected word line is activated in writing.
According to this configuration, a period of time to activate the word line can be used sufficiently for writing on a memory cell, which leads to a further increase in the operating speed of the semiconductor memory device.
In the semiconductor memory device of the present invention, it is preferable that the device includes a plurality of sense amplifier driving circuits, each of which generates a driving signal in accordance with a decode signal in writing, and the driving signal that corresponds to a memory cell to be written is generated at an earlier time than that for reading, while the driving signal that corresponds to a memory cell to be refreshed is generated at the same time as that for reading.
According to this configuration, even if there is a memory cell to be refreshed in memory cells to be written, the high-speed writing of the present invention can be performed on the memory cells to be written while performing a refreshing operation.
In the semiconductor memory device of the present invention, it is preferable that the driving signal that corresponds to the memory cell to be written is generated before a selected word line is activated for writing.
According to this configuration, a period of time to activate the word line can be used sufficiently for writing on a memory cell, which leads to a further increase in the operating speed of the semiconductor memory device.
In the semiconductor memory device of the present invention, it is preferable that a wire is provided in the boundary region between the memory cell to be written and that to be refreshed in writing, the wire having a fixed potential and extending in the bit line direction.
This configuration can suppress the influence of noise that is caused during amplification of the bit line connected to the memory cell to be written upon the bit line connected to the memory cell to be refreshed.
In the semiconductor memory device of the present invention, it is preferable that the memory cell is a 2T/1C memory cell including two switching transistors, each of which is connected to the storage capacitor at one end.
This configuration can perform an interleaving operation between the two switching transistors, which leads to a further increase in the operating speed of the semiconductor memory device.


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