Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-09-05
2003-06-03
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S210130, C365S209000, C365S226000, C365S229000
Reexamination Certificate
active
06574133
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-269223 filed on Sep. 5, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and, more particularly, to a nonvolatile ferroelectric memory device.
Semiconductor memory is currently used in all electric products including main memory devices of large-scale computers, personal computers, household electric appliances, cellular phones and others.
Various kinds of semiconductor memory such as volatile DRAM (dynamic RAM), SRAM (static RAM), nonvolatile MROM (mask ROM), flash EEPROM (electrically erasable programmable memory), and so on, are commercially available. Among those, DRAM is volatile but currently occupies almost all of the market because of its advantages in the sense of its cell area being ¼ as compared with SRAM and its speediness equivalent to flash EEPROM.
On the other hand, since electrically erasable programmable flash EEPROM is nonvolatile, it permits cut of power. However, it involves such drawbacks that, for example, the rewritable frequency (W/E frequency) is in the order of only 10
6
, and therefore it takes the order of micro seconds for writing and a high voltage (12V through 22V) is required for writing, its market is not yet so wide as that of DRAM.
In contrast, nonvolatile memory using a ferroelectric capacitor (ferroelectric memory) has been under development by various manufacturers since it was proposed in 1980 because it has advantages, namely, nonvolatility, rewritable frequency as high as 10
12
, read and write time equivalent to that of DRAM, operability under 3V through 5V, and so on, and it might possibly replace the entire memory market.
FIG. 18
shows a conventional ferroelectric memory cell MC
1
having one-transistor and one-capacitor, its cell array, sense amplifier and dummy cell circuit.
FIG. 19
is a timing chart showing their behaviors.
As apparent from
FIG. 18
, each memory cell of the conventional ferroelectric memory is made up of a transistor and a capacitor connected in series. A cell array is a matrix arrangement of such memory cells, and includes bit lines/BL, BL for reading data, word lines WL
0
, WL
1
for selecting a memory cell transistor, and plate lines PL
0
, PL
1
each for driving one end of a ferroelectric capacitor. The sense amplifier is connected to the bit lines, and the dummy cell circuit is disposed symmetrically to the memory cell.
Behaviors of the ferroelectric memory are explained with reference to FIG.
19
.
In an active mode where the memory cell MC
1
, for example, has been selected, the word line WL
0
connected to MC
1
is HIGH and the plate line PL
0
is HIGH. As a result, memory cell data is read out to one of a pair of bit lines pre-charged to VSS. In case of this example, cell data is read out to the bit line /BL (/BLSA), and the potential of the bit line rises. If the memory cell data is “1”, then polarization of the ferroelectric capacitor is reversed, and the bit line is raised to a high potential. If the memory cell data is “0”, then polarization reversal does not occur, but potential of the bit line rises as much as the paraelectric component of the ferroelectric capacitor and the capacitance ratio of the bit line capacitance.
In this manner, although the bit line potential rises from Vss for both data “1” and “0”, there is a difference between the potentials. Therefore, if the reference bit line BL (BLSA) can be adjusted to an intermediate potential between those potentials, it is possible to determine whether the cell data is “1” or “0” by amplifying the difference between the bit line and the reference bit line with the sense amplifier.
Conventionally, potential of the reference bit line was generated using a dummy cell circuit as shown in FIG.
18
. In a standby mode, the transistors Q
1
and Q
2
, in which dummy word lines SWL
0
, DWL
1
are connected to gates, are turned OFF, and one end N
1
of the paraelectric capacitor C
1
is pre-charged to the source potential of Q
3
, i.e. Vss, by turning the transistor Q
3
ON. In an active mode, a transistor of a dummy word line connected to the reference bit line, which is the transistor Q
1
in this example, is turned ON to connect BL and N
1
, and then the potential of the dummy plate line, which is the other end of C
1
, is raised from Vss to VDC potential. Through these operations, potential Vref of reference BL can be raised from Vss to the intermediate potential between those corresponding to “1” and “0” data by coupling of the paraelectric capacitor C
1
.
However, the dummy cell circuit system of
FIG. 18
, reviewed above, involved the following problems. For example, in the 0.5 &mgr;m rule class, the bit line capacitance CB is about 1000 fF. In case a memory cell capacitor having the area of 3 &mgr;m
2
is used, if the potential at the HIGH side of the bit line amplitude is 3V (=Vaa), then the read-out potential to the bit line of “1” data is about 1.2 V in average of all cells whereas the read-out potential to the bit line of “0” data is about 0.4 V in average of all cells. Therefore, 0.8 V is required as the reference bit line potential, and taking account of fluctuation of ferroelectric capacitors, a reference potential to the level of 1.5 V (=½ Vaa) including estimation for distribution is required.
In order to generate the reference bit line potential of ½ Vaa by using the conventional dummy cell circuit shown in
FIG. 18
, a very large paraelectric capacitor is required. Its reason will be explained below.
FIG. 20
shows value of reference bit line potential Vref under the condition in which the capacitance of the paraelectric capacitor C
1
of the dummy cell circuit is CD, bit line capacitance is CB, and source potential for the dummy cell is VDC ((0<VDC≦Vaa): here let the maximum value be Vaa). The reference bit line potential is a value obtained by dividing VDC×CD, which is the charge of the surplus for raising the paraelectric capacitor CD from Vss to VDC, by the total capacitance (CB+CD). Therefore, to obtain ½ Vaa potential, a large paraelectric capacitor capacitance CD (=1000 fF) equal to the bit line capacitance CB is required. Then, if MOS capacitors of 8 nm are used, a dummy cell capacitor as large as 225 &mgr;m
2
is required, and the chip size will increase significantly. More specifically, to generate Vref of 1 V, capacitance as large as CD=½CB is required, and to generate of Vref of ½ Vaa or more, CB<CD. Thus, CD itself becomes a load capacitance, and there is a large difficulty.
These problems were conventionally avoided by using two other methods.
On of these methods uses a ferroelectric capacitor used in a memory cell to make up such a dummy capacitor without using a paraelectric capacitor such as MOS capacitor having a small dielectric constant. With this method, since the ferroelectric material has a very large dielectric constant, a small dummy cell circuit can be realized.
This method, however, involves the following drawbacks, among others,
1) capacitance value of the ferroelectric capacitor itself largely fluctuates;
2) the ferroelectric capacitor changes in value due to fatigue if it is subjected to polarization reversal;
3) capacitance value of the ferroelectric material decreases when polarization takes place; and
4) characteristic of the ferroelectric capacitor changes due to generation of imprint. So, it is preferable that the paraelectric capacitor is usable.
The second of those methods raises the plate potential in the read-out mode to bring about polarization reversal of the memory cell and read out a signal, and uses the bit line potential after being lowered to Vss as the read-out potential.
In this case, since the plate line potential returns to the original value beforehand, there is the effect that no paraelectric component of the memory cell capacitor i
Kabushiki Kaisha Toshiba
Tran Andrew Q.
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