Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-07-19
2003-12-16
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S751000, C257S763000, C257S764000
Reexamination Certificate
active
06664640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a via hole (a through hole) which is formed penetrating through a semiconductor substrate so as to be electrically connected to a reverse of the substrate, or a semiconductor device having a plated heat sink (abbreviated to “PHS”) layer for heat radiation and stress alleviation at a reverse of the semiconductor substrate.
2. Description of the Related Art
In an analog integrated circuit of a high frequency or a high output amplifying device made of a field-effect transistor (FET), a hetero-bipolar transistor (HBT) or the like, there are formed a via hole (a through hole) penetrating a substrate and a penetrating metal of an electric conductor inside of the via hole in order to ground from a circuit device formed on the semiconductor chip with a low impedance, and thus, they are electrically connected to a back electrode disposed over the entire reverse of the semiconductor chip, thereby achieving the grounding.
In this case, although a metal wire may be used for the purpose of the grounding, the wiring becomes long, so that an inductance component or a resistance component is increased, resulting in abnormal oscillation in an unstable state.
In view of this, the semiconductor chip is connected directly to the back electrode through the substrate at a short distance for the purpose of the grounding, thereby suppressing the component of the inductance or resistance to a low level. Thereafter, the semiconductor chip is securely bonded at the metallic reverse thereof to a metallic surface of a package substrate, a package or the like with a metallic soldering material (a solder), thus ensuring the grounding.
In the meantime, a wiring pad provided on the semiconductor chip and a terminal of the package substrate, the package are connected to each other by bonding via a metal wire.
The structure of a semiconductor apparatus having such via hole is disclosed in, for example, Japanese Unexamined Patent Publication (KOKAI) Nos. 59-117171, 61-79261 and 5-47937.
FIG. 7
is a cross-sectional view schematically showing the structure of a semiconductor apparatus (a semiconductor chip) shown in the prior art; and
FIG. 8
is a cross-sectional view illustrating the state in which the semiconductor chip in the prior art, shown in
FIG. 7
, is bonded to a package metal mount such as a package with a soldering material.
In the semiconductor chip shown in
FIG. 7
, a semiconductor device of a field-effect transistor (FET) is disposed at the obverse of a semiconductor substrate
1
made of semi-insulating GaAs.
That is to say, a device region formed of an n-type GaAs conductive layer
2
is disposed at the obverse of the semiconductor substrate
1
made of semi-insulating GaAs. Furthermore, on the GaAs conductive layer
2
are formed a Schottky gate electrode
5
, and a source electrode
3
and a drain electrode
4
which sandwich the gate electrode
5
therebetween. The semiconductor device is covered with an insulating film
7
made of SiO
2
or the like.
Moreover, a through a hole (i.e., via hole)
6
penetrating the semiconductor substrate
1
from the obverse thereof down to the reverse thereof is formed near the source electrode
3
. As penetrating metals for connecting so as to ground the source electrode
3
to the reverse are laminated a titanium (Ti) layer
9
, a gold (Au) layer
10
and an Au-plating layer
12
on the inner wall of the via hole
6
.
On the other hand, a Ti layer
30
, an Au layer
31
and an Au-plating layer
32
are laminated in this order in contact with the penetrating metals of the via hole
6
as a back electrode also over the entire reverse of the semiconductor substrate
1
.
FIG. 8
illustrates an example of the arrangement in which the Au-plating layer
32
at the reverse of the semiconductor chip shown in
FIG. 7
is bonded onto a metal mount having a package, a lead frame, a package substrate with a soldering material
18
made of gold tin (AuSn) or the like. The metal mount is made of copper (Cu) plated with Au.
Here, the source electrode
3
is connected to the back electrode via the penetrating metal of the via hole
6
, and further, the back electrode is connected to a metal mount
19
via the conductive soldering material
18
. Consequently, the source electrode
3
is grounded to the earth.
Each of the Ti layers
9
and
30
used herein is formed so as to enhance a contact property since Au is poor in contact property with respect to the semiconductor substrate. In addition, each of the Ti layers
9
and
30
is formed as thinly as, for example, in about 100 nm so as not to increase resistance.
In other words, the Ti layers in the above-described prior art never have the function of a barrier layer, which is used according to the present invention, described later.
In the meantime, the Au layer
31
laminated on the Ti layer
30
is formed as a power supplying layer for applying Au plating in the thickness of about 100 to 500 nm. The Ti layer and the Au layer are formed by sputtering vapor deposition or electron gun vapor deposition.
The wiring at the obverse and the Au-plating layer
32
of the penetrating metal are formed in the thickness of about 0.5 &mgr;m to 30 &mgr;m. Only the Au layer
31
formed by the vapor deposition can secure conductivity without using Au-plating layer
32
.
Additionally, the thickness of the Au layer
31
or the Au-plating layer
32
in the back electrode approximately ranges from 0.5 &mgr;m to 30 &mgr;m. Since a device of low power consumption for low noise amplification or the like is enough to merely secure the close contact with the soldering material, the Au layer
31
or the Au-plating layer
32
is formed in the thickness of about 0.5 &mgr;m by the sputtering vapor deposition or the like without applying any Au plating.
In contrast, the Au-plating layer
32
is thickly formed in a device of high power consumption for high output amplification.
Otherwise, in the above-described prior art, it is necessary to thin the semiconductor substrate in order to enhance a heat radiating property in a semiconductor device of large heat generation. Therefore, it is general to dispose a heat sink layer having a heat radiating function at the reverse of the semiconductor substrate in order to reinforce the physical strength of a chip or alleviate a stress in the case in which a stress occurs between the semiconductor substrate and the metal mount or the soldering material caused by expansion of the semiconductor substrate. Such a heat sink layer is called also a PHS (plated heat sink) layer.
In general, although gold (Au), which is soft and excellent in heat conductivity and electric conductivity, has been mostly used as such a heat sink layer, copper (Cu), which is inexpensive, soft and excellent in heat conductivity and electric conductivity, has been used in recent years.
In the prior art, gold tin (Au—Sn) composed of gold added with about 20% of tin has been mostly used as the soldering material for fixing the semiconductor chip to the metal mount in the case where the heat sink layer requires the reliability, and the melting point of the soldering material for fixing the semiconductor chip is set to as high as 300° C. to 400° C. since there are heating works thereafter such as heating in bonding, cap sealing for the package, formation of a mold resin or soldering of the package to a circuit board. As the soldering material may be used a lead tin (Pb—Sn) or zinc tin (Zn—Sn) based soldering material.
Subsequently, explanation will be made on a method for fabricating the semiconductor chip having the via hole and the PHS layer.
FIGS. 9
to
15
are schematically cross-sectional views showing, in sequence, one example of a method for fabricating the semiconductor apparatus in the prior art.
First of all, as shown in
FIG. 9
, the n-type conductive layer
2
is epitaxially grown on the semi-insulating GaAs substrate
1
having the thickness of about 600 &mgr;m. A region except for the device is removed by etching or t
Clark Jasmine
Hayes & Soloway P.C.
NEC Compound Semiconductor Devices Ltd.
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