Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-10-21
2003-04-15
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S635000
Reexamination Certificate
active
06548900
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. Particularly, the present invention relates to a semiconductor device having a multilayer interconnection structure of a buried interconnection, and a fabrication method thereof.
2. Description of the Background Art
As the first conventional art of a semiconductor device having a multilayer interconnection structure of a buried interconnection, the semiconductor device disclosed in Japanese Patent Laying-Open No. 9-153545 is taken by way of example. A fabrication method thereof will be described with reference to FIG.
20
. Referring to
FIG. 20
, an interlayer insulation film
102
such as a silicon oxide film is formed by CVD (chemical vapor deposition) on a silicon substrate
101
. A lower interconnection
104
is formed on interlayer insulation film
102
.
A connection hole stopper film
106
such as a silicon nitride film is formed on interlayer insulation film
102
to cover lower interconnection
104
. A lower interlayer insulation film
108
such as a silicon oxide film is formed by CVD and the like on connection hole stopper film
106
. Then, an upper trench stopper film
109
such as a silicon nitride film is formed on lower interlayer insulation film
108
.
Referring to
FIG. 21
, a resist pattern
112
is formed on upper trench stopper film
109
. Using resist pattern
112
as a mask, upper trench stopper film
109
is subjected to anisotropic etching, whereby a connection hole
113
a
is formed. Then, resist pattern
112
is removed.
Referring to
FIG. 22
, an upper interlayer insulation film
110
such as a silicon oxide film is formed by CVD and the like on upper trench stopper film
109
to fill connection hole
13
a.
Referring to
FIG. 23
, a resist pattern
116
is formed on upper interlayer insulation film
110
. Using resist pattern
116
as a mask, upper interlayer insulation film
110
is subjected to anisotropic etching, whereby an upper interconnection trench
118
that exposes the surface of upper trench stopper film
109
is formed.
By connection hole
113
a
formed in upper trench stopper film
109
, lower interlayer insulation film
109
is etched at the same time in self-alignment, whereby a connection hole
113
b
that exposes the surface of connection hole stopper film
106
is formed. Then, resist pattern
116
is removed. By removing connection hole stopper film
106
exposed at the bottom of connection hole
113
b
, connection hole
113
that exposes the surface of lower interconnection
104
is formed.
Referring to
FIG. 24
, a conductive layer
120
to establish an upper interconnection is formed on upper interlayer insulation film
110
to fill connection hole
113
and upper interconnection trench
118
. Referring to
FIG. 25
, a CMP (chemical mechanical polishing) process or the like is applied to conductive layer
120
, whereby the conductive layer located above the top surface of upper interlayer insulation film
110
is removed to form an upper interconnection
120
in upper interconnection trench
118
. Thus, the main part of the multilayer interconnection structure of a buried interconnection is completed in a semiconductor device.
As the second conventional art, the semiconductor device disclosed in Japanese Patent Laying-Open No. 8-335634 is taken by way of example. The fabrication method thereof will be described hereinafter. Referring to
FIG. 26
, a lower interconnection
104
is formed on a silicon substrate
101
. An interlayer insulation film
122
such as a silicon oxide film is formed by CVD or the like on silicon substrate
101
to cover lower interconnection
104
. A resist pattern
123
is formed on interlayer insulation film
122
.
Referring to
FIG. 27
, interlayer insulation film
122
is subjected to anisotropic etching with resist pattern
123
as a mask, whereby a connection hole
124
that exposes the surface of lower interconnection
104
is formed. Referring to
FIG. 28
, an organic compound layer
125
is applied on interlayer insulation film
122
to fill connection hole
124
. Desirably, the etching rate of organic compound layer
125
by anisotropic etching in forming an interconnection trench described afterwards is not more than ½ the etching rate of interlayer insulation film
122
.
Referring to
FIG. 29
, organic compound layer
125
located above the top surface of interlayer insulation film
122
is removed, so that organic compound layer
125
remains only in connection hole
124
.
Referring to
FIG. 30
, a resist pattern
126
is formed on interlayer insulation film
122
. Referring to
FIG. 31
, interlayer insulation film
122
is subjected to anisotropic etching with resist pattern
126
as a mask, whereby an upper interconnection trench
118
of a predetermined depth is formed. Referring to
FIG. 32
, resist pattern
136
and organic compound layer
125
are removed at the same time.
Referring to
FIG. 33
, a conductive layer (not shown) that becomes the upper interconnection is formed on interlayer insulation film
122
to fill connection hole
124
and upper interconnection trench
118
. By applying a CMP process to that conductive layer, the conductive layer located above the top surface of interlayer insulation film
122
is removed, whereby an upper interconnection
120
is formed in upper interconnection trench
118
. Thus, the main part of the multilayer interconnection structure of a buried interconnection is completed in a semiconductor device.
The conventional semiconductor device obtained by the abovedescribed fabrication method has problems set forth in the following. The problem of the first conventional art is first described. In the actual device, another upper interconnection (not shown) is located in the proximity of upper interconnection
120
shown in FIG.
25
. The two adjacent upper interconnections are both formed right above upper trench stopper film
109
. Upper interlayer insulation film
110
is located between respective side surfaces facing each other of the two upper interconnections.
The capacitance between the two adjacent upper interconnections includes the capacitance of upper trench stopper film
109
in addition to the capacitance of upper interlayer insulation film
110
. This increase in the capacitance between the interconnections causes degradation in the performance of the semiconductor device.
When an upper layer interconnection (not shown) is to be further provided on upper interconnection
120
, a stopper film (not shown) such as a silicon nitride film must be additionally formed right above upper interconnection
120
. This means that the capacitance of this stopper film is added to the capacitance between the two adjacent upper interconnections. As a result, the capacitance between the upper interconnections is further increased.
The problem of the second conventional art will be described hereinafter. Upper interconnection trench
118
filled with the upper interconnection is formed in interlayer insulation film
122
at the step shown in FIG.
31
. When an upper interconnection trench differing in width from that of upper interconnection trench
118
is to be formed, there is a possibility that the upper interconnection trench of the smaller width will be formed with a depth smaller than that of an upper interconnection trench having a larger trench width. The depth of the upper interconnection trench may vary according to the trench width. This causes variation in the resistance of the upper interconnection filling the upper interconnection trench.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a semiconductor device aimed to reduce interconnection capacitance and variation in interconnection resistance.
Another object of the present invention is to provide a method of fabricating such a semiconductor device.
According to an aspect of the present invention, a semiconductor device includes a semiconductor substrate having a main surface, a first int
Clark Sheila V.
McDermott & Will & Emery
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