Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2001-12-04
2003-08-12
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S778000, C257S668000
Reexamination Certificate
active
06605876
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor packaging technology, and more particularly to a semiconductor chip package and a novel connection structure for use in the package, which improves high frequency characteristics of the semiconductor chip package.
2. Description of Related Art
Generally, semiconductor chips are packaged to physically protect the semiconductor chips from external environments. The semiconductor package includes leads that carry electrical input and output signals to and from an external device. Since the operational goal of semiconductor memory chips is to reduce power and increase the speed, the semiconductor package is required to evolve beyond simply providing physical protection. To ensure the memory chip operation with higher performance and improved reliability, it is necessary to design package devices with optimal electrical characteristics. In conventional memory devices operating at low speed, deterioration of function or performance due to parasitic parameters of the package and an RLC circuit of the package substrate has not been considered as critical or significant.
However, certain memory devices capable of performing at very high speeds such as Rambus DRAMs operating at data rates up to 800 million transfers/second and DDR (Double Data Rate) RAMs exhibit all the properties of an RF signal. Phenomena like reflections and crosstalk take on unprecedented importance in the very high frequency memory devices. Further, at the speeds of Rambus, parasitic parameters due to the package may significantly degrade performance of the memory device, potentially causing failures. The three electrical parameters, i.e., capacitance, inductance, and resistance, are inherent in every packaging concept. Resistance may cause signal line DC drops while contributing to charging delays in RC networks. On the other hand, resistance may also reduce undesired noise at a system level. The capacitance of a channel is mainly responsible for signal loss and propagation velocity and can be reduced by reducing the physical dimensions of the RC networks. Inductance also contributes to switching noise and delays associated with packages. A low dielectric constant is favorable both for signal delay and crosstalk, which is the coupled noise from busy signal paths to idle paths caused by mutual capacitive and inductive coupling. If inductance is reduced, a stable power supply, improved crosstalk and decreased signal skew are observed. Capacitance and inductance may be expressed in static parasitic parameters including inductance of signal trace, mutual capacitance and mutual inductance and in dynamic parasitic parameters such as an SSO (Simultaneously Switching Output) noise and crosstalk.
In a substrate having multiple conductive and insulating layers, the capacitance and the inductance are opposing properties in the substrate or connection structure of a package. Therefore, modification of the connection structure to decrease inductance is inevitably accompanied by an increase of parasitic parameters and capacitance.
SUMMARY OF THE INVENTION
The present invention can simultaneously improve inductive and capacitive elements of a connection structure in a semiconductor chip package.
Also, the present invention provides a novel connection structure for ensuring stable electrical characteristics of a semiconductor chip operating at very high frequency.
According to one embodiment of the present invention, an electrical connection structure for electrically connecting a semiconductor chip to an external circuit device is provided. The connection structure comprises: a ground conductive plate connected to ground power of the semiconductor chip; an insulating layer formed on the ground conductive plate; and a signal pattern layer formed on the insulating layer and having signal patterns in electrical communication with the semiconductor chip. The ground conductive plate includes a projected blank pattern that corresponds to the signal pattern layer.
With the present invention, self inductance and mutual inductance of the connection structure is reduced. Further, because of the blank patterns formed in the proximal ground plate, the capacitance is also reduced. Therefore, both the switching output noise and cross talk is simultaneously prevented in very high frequency operation and hence electrical characteristics and performance are significantly improved in package devices such as wafer level packages and ball grid array packages operating at high data rates.
According to another embodiment of the present invention, an electrical connection structure for electrically connecting a semiconductor chip to an external circuit device comprises: a ground conductive plate connected to ground power of the semiconductor chip; an insulating layer formed on the ground conductive plate; a signal pattern layer formed on the insulating layer and having signal patterns communicating electrical signals with the semiconductor chip. The ground conductive plate, the insulating layer and the signal pattern are stacked sequentially. The signal pattern layer includes a chip connection portion electrically connected to the semiconductor chip, an external connection portion electrically connected to the external circuit device and a pattern line portion for electrically connecting the chip connection portion with the external connection portion. The ground conductive plate includes blank patterns having shapes corresponds to at least one of the chip connection portion, the external connection portion and the pattern line portion.
The connection structure of the present invention can be applied to a wafer level package that is assembled in a batch wafer process for fabricating on-chip circuits of semiconductor chips on a silicon wafer, or applied to a ball grid array package.
These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of this invention that are not specifically illustrated.
REFERENCES:
patent: 5983493 (1999-11-01), Eldridge et al.
patent: 6194778 (2001-02-01), Ohsawa et al.
Chang Tae-Sub
Lee Dong-Ho
Marger & Johnson & McCollom, P.C.
Rose Kiesha
Samsung Electronics Co,. Ltd.
Zarabian Amir
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