Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-10-01
2003-07-29
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S025000, C714S031000, C714S726000, C710S106000
Reexamination Certificate
active
06601189
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to communication protocols and interfaces, and more specifically, to a system and method for communicating with an integrated circuit.
2. Related Art
System-on-chip devices (SOCs) are well-known. These devices generally include a processor, one or more modules, bus interfaces, memory devices, and one or more system busses for communicating information. Because multiple modules and their communications occur internally to the chip, access to this information is generally difficult when problems occur in software or hardware. Thus, debugging on these systems is not straightforward. As a result of development of these SOCs, specialized debugging systems have been developed to monitor performance and trace information on the chip. Such systems typically include dedicated hardware or software such as a debug tool and debug software which accesses a processor through serial communications.
However, debugging an SOC generally involves intrusively monitoring one or more processor registers or memory locations. Accesses to memory locations are sometimes destructive, and a data access to a location being read from a debugging tool may impede processor performance. Similarly, accesses are generally performed over a system bus to the processor, memory, or other module, and may reduce available bandwidth over the system bus for performing general operations. Some debugging systems do not perform at the same clock speed as that of the processor, and it may be necessary to slow the performance of the processor to enable use of debugging features such as obtaining trace information. By slowing or pausing the processor, some types of error may not be reproduced, and thus cannot be detected or corrected. Further, accurate information may not be available altogether due to a high speed of the processor; information may be skewed or missing.
Some systems include one or more dedicated functional units within the SOC that are dedicated to debugging the processor, sometimes referred to as a debug unit or module. However, these units affect the operation of the processor when obtaining information such as trace information. These units typically function at a lower speed than the processor, and thus affect processor operations when they access processor data. For example, when transmitting trace information off-chip, trace information may be generated at a rate that the debug module can process or transmit off-chip, and the processor must be slowed to avoid losing trace information. The debug module relies upon running debug code on the target processor itself, and this code is usually built into the system being debugged, referred to as the debugee. Thus, the presence of the debug code is intrusive in terms of memory layout, and instruction stream disruption.
Other debugging systems referred to as in-circuit emulators (ICEs) match on-chip to hardware and are connected to it. Thus, on-chip connections are mapped onto the emulator and are accessible on the emulator which is designed specifically for the chip to be tested.
However, emulators are prohibitively expensive for some applications because they are specially-developed hardware, and do not successfully match all on-chip speeds or communications. Thus, emulator systems are inadequate. Further, these systems generally transfer information over the system bus, and therefore necessarily impact processor performance. These ICEs generally use a proprietary communication interface that can only interface with external debug equipment from the same manufacturer.
Another technique for troubleshooting includes using a Logic State Analyzer (LSA) which is a device connected to pins of the integrated circuit that monitors the state of all off-chip communications. LSA devices are generally expensive devices, and do not allow access to pin information inside the chip. In sum, there are many systems which are inadequate for monitoring the internal states of a processor and for providing features such as real-time state and real-time trace in a non-intrusive manner.
Further, some debugging circuits make use of an interface referred in the art to as a JTAG (Joint Test Action Group) interface defined by IEEE 1149.1-1990 standard entitled Standard Test Access Port and Boundary-Scan Architecture. The specification was adopted as an IEEE standard in February 1990, and JTAG interfaces are commonly provided in integrated circuit systems. IEEE standard 1149.1 allows test instructions and data to be serially loaded into a device and enables the subsequent test results to be serially read out. JTAG interfaces are provided to allow designers to efficiently access internal parameters of integrated circuits to perform a boundary scan test on an integrated circuit (IC) device to detect faults in the IC. Boundary scan testing is well-known in the art of IC and ASIC development.
Every IEEE standard 1149.1-compatible device includes an interface having four additional pins—two for control and one each for input and output serial test data. To be compatible, a component must have certain basic test features, but IEEE standard 1149.1 allows designers to add test features to meet their own unique requirements. Some systems provide a method by which a JTAG interface associated with an integrated circuit may be reused to transfer debugging information. In one approach, a single JTAG instruction is used to place the JTAG port into a mode whereby JTAG pins are reused to form a link between the integrated circuit and another system. Signals on the JTAG pins in this mode are not conformant with the IEEE 1149.1 JTAG standard, nor do they obey any of the JTAG standard rules and thus cannot be connected to a standard JTAG device. In addition, the JTAG interface is a low-speed link, and is generally not capable of transferring information at a high rate of speed (in the MBit/s range of transmission and higher). Thus, an improved interface is needed for accessing an integrated circuit.
SUMMARY OF THE INVENTION
These and other drawbacks of conventional debug systems are overcome by providing an interface and protocol for communicating with an integrated circuit.
Further, a high-speed link is provided for obtaining information from an integrated circuit. Because the interface operates at a high rate of speed, real-time collection of trace information is possible. Further, the trace information transferred includes all of the information that an external system would use for debugging a processor. Also, the link may be memory-mapped such that an on-chip processor or other device associates with the integrated circuit may execute software located on the external system and on-chip devices may perform system bus transactions with a memory or storage device of the external system. In one aspect, the system includes an interface protocol that provides flow control between an integrated circuit and external system without requiring additional flow control pins.
According to another aspect of the invention, trace information communicated over the interface includes both address information and message information. In another aspect, the trace information includes timing information.
In another aspect of the invention, the link operates at a rate which is proportional to an operating rate of a processor system bus. In one aspect, the rate of the link changes as the rate of the system bus changes. Thus, debug information generated on-chip will not overwhelm the transmission capabilities link because the link speed is derived from the internal system bus rate.
In another aspect of the invention, an external system is capable of stopping, starting, and resetting the processor through the external link. In one embodiment, signals are provided for controlling the processor. In another embodiment, the external system is capable of writing to a register in a debug circuit to effect processor control.
In another aspect, the trace information may be compressed by the trace system. By compressing information, trace informatio
Edwards David Alan
Ramanadin Bernard
Rich Anthony Willis
Beausoliel Robert
Jorgenson Lisa K.
Maskulinski Michael
Morris James H.
STMicroelectronics Limited
LandOfFree
System and method for communicating with an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for communicating with an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for communicating with an integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3104552