Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-08-09
2003-09-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S081000, C326S083000, C326S062000, C327S333000, C345S092000, C345S094000, C345S096000, C345S204000, C345S211000
Reexamination Certificate
active
06617878
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage level shifter and a display device incorporating such a voltage level shifter. Such a shifter may, for example, be used in large area silicon-on-insulator (SOI) circuits for interfacing with signals of smaller amplitudes. An example of such an application is monolithic driver circuitry for flat-panel matrix displays, such as liquid crystal displays, fabricated with low temperature poly-silicon thin-film transistors (TFTs) whore interfacing between signal levels of 3.3 to 5 volts and signals of 10 to 20 volts is often required.
2. Description of the Related Art
FIG. 1
of the accompanying drawings illustrates a known type of CMOS inverter, for example as disclosed in A. Bellaouar, M. Elmasry, “Low Power Digital VLSI Design”, Kluwer Academic Publishers, 1995, which may be used to provide a limited range of level shifting. The inverter comprises a P-type transistor T
1
and an N-type transistor T
2
connected in series between a power supply line vdd and ground gnd. The drains of the transistors T
1
and T
2
are connected to an output !OUT for providing inverted output signals and the gates of the transistors are connected together to input IN.
A disadvantage of such an arrangement for implementation in TFT circuits is that the input voltage level must be greater than the switching point. However, this condition is difficult to achieve with low performance transistors having highly variable transistor characteristics. For example, typical signal levels produced in conventional large scale integrated circuits as used in active matrix liquid crystal display (AMLCD) interface circuitry range from 2.7 to 5.5 volts. The switching point of the inverter should range from 1.35 to 2.5 volts depending on the desired noise margin.
FIG. 2
of the accompanying drawings illustrates a typical switching characteristic of a CMOS inverter of the type shown in
FIG. 1
as a function of the transistor characteristics and the supply voltage Vdd. The switching point V
th
of the inverter is defined as the input voltage at the intersection of Vin=Vout and is given by:
V
t
h
=
V
T
h
+
β
p
β
n
(
V
d
d
-
|
V
T
p
|
)
1
+
β
p
β
n
where &bgr;
p
and &bgr;
n
are the transconductances and V
tp
and V
tn
are the threshold voltages of the P-type transistor T
1
and the N-type transistor T
2
, respectively.
The range of transistor parameters for which the inverter will switch with a given input voltage defines a “process margin”. As illustrated by the above expression, in order to achieve low input voltage operation, it is necessary to ensure a low threshold voltage and a high mobility of the N-type transistor T
2
. Also, the switching point of the inverter increases with the supply voltage Vdd. In order to improve the performance of level shifters based on such inverters, it is known to connect several inverters in series and to apply different supply voltages to the inverters. However, level shifters of this type are not suitable for applications in which the transistor performance is not well defined and where a large signal level shift is required.
Another known type of level shifter is shown in
FIG. 3
of the accompanying drawings and in based on differential techniques as used, for example, in sense amplifiers of memory circuits. Such a CMOS sense amplifier is also disclosed in Bellaouar at al (see above) and comprises P-type transistors T
3
and T
4
and N-type translators T
5
, T
6
and T
7
. The transistors T
5
and T
6
form a differential pair with the transistor T
7
acting as a tail current source with its gate connected to a terminal Vb for receiving a bias voltage. The transistors T
3
and T
4
are connected between the drains of the transistors T
5
and T
6
, respectively, and the supply line vdd. The gate of the transistor T
3
is connected to the drains of the transistors T
4
and T
6
and to an output terminal OUT whereas the gate of the transistor T
4
is connected to the drains of the transistors T
3
and T
5
and to an output terminal !OUT for supplying inverted output signals. The gates of the transistors T
5
and T
6
are connected to complementary inputs IN and !IN for receiving complementary input signals.
Assuming that the transistors are perfectly matched and identical differential input voltages ate supplied to the inputs IN and !IN, the tail current set by the bias voltage flows in equal portions through the transistors T
5
and T
6
and hence through the transistors T
3
and T
4
. This condition is meta-stable and changes in response to any perturbations of the differential input voltage. For example, if the voltage at the input IN is slightly larger than that at the input !IN, the transistor T
5
turns on more than the transistor T
6
. This has the effect of lowering the voltage at the output !OUT. The transistor T
4
is turned on more which increases the voltage at the output OUT. The transistor T
3
is turned off further, which lowers the voltage at the output !OUT and increases the voltage at the output OUT. Thus, a slight imbalance in the input voltages is sensed and amplified at the output terminals !OUT and OUT.
A limitation of this type of circuit as a level shifter is that it requires that the logic high input levels supplied to the inputs be significantly higher than the threshold voltages of the N-type transistors. However, when embodied as a monolithic integrated circuit driver for an AMLCD, the threshold voltages of the N-type transistors can be as high as 4.5 volts.
For more efficient operation at lower input voltages, the conduction types of the transistors may be reversed to provide an arrangement as illustrated in
FIG. 4
of the accompanying drawings, thus, the transistors T
3
and T
4
are N-type transistors whereas the transistors T
5
, T
6
and T
7
are P-type transistors. However, a disadvantage of this arrangement in that, when a high supply voltage Vdd and low input voltages are used, the transistors T
5
and T
6
operate in the linear regime. Differential amplifiers are much more efficient when the input transistors are operated in the saturated regime. In this condition, the difference in currents is greatest for a given differential input voltage so that the gain is higher for a given tail current.
FIG. 5
of the accompanying drawings illustrates another known type of level shifter in the form of a source follower, P-type transistors T
8
and T
9
are connected in series between the supply line vdd and ground gnd. The drain of the transistor T
8
is connected to the source of the transistor T
9
and to an output OUT. The gate of the transistor T
8
is connected to receive the bias voltage Vb and the gate of the transistor T
9
is connected to an input terminal IN, when the transistors T
8
and T
9
are in saturation, the output voltage is shifted positively by (VDD−Vb), assuming that the transistors T
8
and T
9
are matched. Two such level shifters may be used to drive a differential amplifier of the type shown in
FIG. 3
or
4
in order to solve the problem of high N-type device threshold voltage or to maintain P-type devices in saturation. However, a disadvantage of such an arrangement arises from the many DC current paths.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, there is provided a voltage level shifter comprising first and second voltage followers arranged to receive bias voltages from the second and first voltage followers, respectively.
According to a second aspect of the invention, there is provided a voltage level shifter comprising first to fourth transistors of a first conduction type, the first and second transistors being connected in series between first and second power supply inputs with the control electrode of the second transistor being connected to a first input for receiving a
Brownlow Michael James
Cairns Graham Andrew
Kubota Yasushi
Washio Hajime
Conlin David G.
Daly, Jr. William J.
Edwards & Angell LLP
Sharp Kabushiki Kaisha
Tan Vibol
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