Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-25
2003-08-19
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S929000
Reexamination Certificate
active
06608352
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a system for determining the thermal resistance of a field effect transistor formed in SOI (semiconductor on insulator) technology.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET
100
are scaled down further, the junction capacitances formed by the drain and source extension junctions
104
and
106
and by the drain and source contact junctions
108
and
112
may limit the speed performance of the MOSFET
100
. Thus, referring to
FIG. 2
, a MOSFET
150
is formed with SOI (semiconductor on insulator) technology. In that case, a layer of buried insulating material
152
is formed on the semiconductor substrate
102
, and a layer of semiconductor material
154
is formed on the layer of buried insulating material
152
. A drain region
156
and a source region
158
of the MOSFET
150
are formed in the layer of semiconductor material
154
. Elements such as the gate dielectric
116
and the gate electrode
118
having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function. Processes for formation of such elements
116
,
118
,
152
,
154
,
156
, and
158
of the MOSFET
150
are known to one of ordinary skill in the art of integrated circuit fabrication.
In
FIG. 2
, the drain region
156
and the source region
158
are formed to extend down to contact the layer of buried insulating material
152
. Thus, because the drain region
156
, the source region
158
, and a channel region
160
of the MOSFET
150
do not form a junction with the semiconductor substrate
102
, junction capacitance is minimized for the MOSFET
150
to enhance the speed performance of the MOSFET
150
formed with SOI (semiconductor on insulator) technology, as known to one of ordinary skill in the art of integrated circuit fabrication.
The buried insulating material
152
is comprised of a dielectric material such as silicon dioxide (SiO
2
) according to one embodiment of the present invention. The buried insulating material
152
has lower heat conductivity (about 100 times lower) than semiconductor material such as silicon for example. During operation of the MOSFET
150
, the MOSFET
150
dissipates power as the MOSFET
150
is biased to conduct current. Such dissipation of power heats up the layer of semiconductor material
154
. Because the buried insulating material
152
has lower heat conductivity, the power dissipated by the MOSFET
150
builds up within the layer of semiconductor material
154
, and the layer of semiconductor material
154
may heat up to temperatures that degrade the performance of the MOSFET
150
according to the SHE (Self Heating Effect), as known to one of ordinary skill in the art of integrated circuit fabrication.
For designing integrated circuits having the MOSFET
150
formed in SOI (semiconductor on insulator) technology, the SHE (Self Heating Effect) is typically modeled with a thermal resistance R
th
, as known to one of ordinary skill in the art of integrated circuit fabrication. The thermal resistance R
th
is the rate of change in temperature of the layer of semiconductor material
154
, &Dgr;T, with respect to a rate of change in power dissipation, &Dgr;W, by the MOSFET
150
, as known to one of ordinary skill in the art of integrated circuit fabrication:
R
th
=&Dgr;T/&Dgr;W
The prior art mechanisms for determining the self heating effect, as described in
Measurement of I-V Curves of Silicon
-
on
-
Insulator
(SOI)
MOSFET's Without Self
-
Heating
, by K. A. Jenkins and J. Y.-C Sun, IEEE Electron Device Letters, Vol. 16, No. 4, April 1995 or
Self
-
Heating Effects in SOI MOSFET's and Their Measurement by Small Signal Conductance Techniques
by Bernard M. Tenbroek et al., IEEE Transactions on Electron Devices, Vol. 43, No. 12, December 1996, use a pulse technique or a small signal conductance technique that are relatively complicated and time-consuming. Nevertheless, the thermal resistance R
th
is a parameter that is used for designing integrated circuits having MOSFETs in SOI (semiconductor on insulator) technology. Thus, a mechanism is desired for determining the thermal resistance R
th
of a MOSFET formed in SOI (semiconductor on insulator) technology in an easy yet accurate manner.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a p-n junction is formed from a drain region or a source region of a field effect transistor formed with a semiconductor film on a buried insulating layer in SOI (semiconductor on insulator) technology. The current versus temperature characteristic of the p-n junction is determined. From such a current versus temperature characteristic, the temperature of the field effect transistor at various power dissipation levels is determined. The thermal resistance R
th
parameter for the field effect transistor is determined to be the rate of change of the temperature of the field effect transistor with respect to the rate of change of power dissipation level of the field effect transistor.
In one embodiment of the present invention, the thermal resistance R
th
parameter is determined for a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology
Lee Michael
Long Wei
Choi Monica H.
Nhu David
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