Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-01
2003-12-23
Fahmy, Jr., Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000
Reexamination Certificate
active
06667502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention generally relates to capacitors for semiconductor circuit memory storage devices. More particularly, the present invention relates to highly stable, robust capacitor structures in semiconductor circuit memory storage devices.
2. The Relevant Technology
In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge in spite of parasitic capacitances and noise that may be present during circuit operation. The ability to maintain required storage node capacitance levels in densely packed storage cells is particularly important as the density of DRAM arrays continues to increase for the foreseeable future generations of memory devices.
One known method for maintaining, as well as increasing, storage node size in densely packed memory devices is through use of self-aligned stacked-capacitor cells for 64-MB DRAMs formed as three-dimensional cylindrical container structures.
FIG. 1A
illustrates conventional double-sided cylindrical container structures
10
configured as a double crown structure. The cylindrical capacitor container structures
10
are formed over a first dielectric layer
1
that lies on a semiconductor substrate
12
. Each of the cylindrical capacitor container structures
10
are connected to one of the source and drain impurity regions
14
and
14
′ of one of the transistors
13
via a conductive plug
15
. The container structures
10
are double-sided in that poly cylinders
16
have a conductively doped hemispherical grain (HSG) poly layer
17
formed on both the inside and outside thereof, and a capacitor dielectric film
18
surrounds the entire surface HSG layer of the storage node electrode. Then, a top capacitor electrode
19
, such as poly, is formed to complete the storage cell
10
.
Referring now to
FIG. 1B
which shows a portion of the process for fabricating the
FIG. 1A
conventional cylindrical container structures, a second dielectric layer
2
is formed on the first dielectric layer
1
, and a via hole
3
is formed through the second dielectric layer
2
in alignment with the plug
15
previously formed in the first dielectric layer
1
, and then the polysilicon layer
16
is deposited on the cylindrical walls of the via hole. The polysilicon is removed from the upper surface of the second dielectric layer
2
by planarization (e.g., CMP) to yield the intermediate structure shown in FIG.
1
B. In the next process step, the second dielectric layer
2
is selectively etched away until the first dielectric layer
1
and plug
15
is reached with the resulting structure as shown in
FIG. 1C. A
free standing cylindrical structure
16
is left exposed without structural support over the first dielectric layer
1
after removing the second dielectric layer
2
. In further processing, the HSG
17
, capacitor dielectric film
18
and electrode
19
are sequentially formed on the cylinder structures
10
to yield the double crown structure (double container cell) shown in FIG.
1
A.
In
FIGS. 2A-2D
, a conventional fabrication scheme is shown for fabricating capacitor studs used in a high density array. In fabricating the conventional stud structures, as shown in
FIG. 2A
, via holes
27
are formed through a second dielectric layer
26
which is provided over a first dielectric layer
21
arranged on a semiconductor substrate
22
. The substrate
22
has a transistor
23
including source and drain regions
24
and
24
′, and one of which is connected to the via holes
27
via conductive plug
25
. After the via hole
27
is formed through the second dielectric layer
26
in alignment with the plug
25
previously formed in the first dielectric layer
1
, a metal or other conductive material
28
is deposited so as to fill the via hole
27
and form the stud
28
. The metal is removed from the surface of the second dielectric layer
26
by planarization (e.g., CMP) to yield the intermediate structure shown in FIG.
2
B. In the next process step, the second dielectric layer
26
is selectively etched away until the first dielectric layer
21
and plug
25
is reached with the resulting structure as shown in
FIG. 2C. A
free standing stud structure
28
is left exposed without structural support over the first dielectric layer
21
after removing the second dielectric layer
26
. In further processing, the studs
28
have a conductively doped hemi-spherical grain (HSG) poly layer
200
formed on their exterior profile, and a capacitor dielectric film
201
surrounds the entire surface HSG layer
200
of the storage node electrode. Then, a top capacitor electrode
202
, such as polysilicon, is formed to complete the storage cell
20
.
The present inventors have determined that the yields of double-sided container or stud structures in high density memory arrays such as illustrated in
FIGS. 1A and 2D
above, respectively, has been lowered because of falling problems with the containers or studs that occur during device fabrication. Namely, the containers and studs are susceptible to falling over and breaking during etch back (i.e., removal of the second dielectric layer) or other further processing operations such as deposition of the capacitor dielectric film. The conventional studs or containers have relatively high sidewalls and a relatively small supporting “footprint” and thus do not have a strong foundation at their bottoms. Consequently, they are very susceptible to toppling over when subjected to handling and/or processing forces. Nonetheless, as demand for reduced feature size continues, there remains a need to fabricate very tall studs (e.g., 1.5 &mgr;m) and tall double sided containers with relatively small “footprints”. However, the fabrication of taller studs (i.e., larger height-to-width (H/W) structures) exacerbates the falling problem as a given base dimension must support even taller walls. When the conventional stud or container structures fall over they can short to an adjacent storage node poly, which will render the adjacent storage cells shorted out. In a 64 M DRAM, for instance, even if there were only one out of 100 K cells that had a short due to such falling, this would cause 640 random failures in the 64 M DRAM. This number of failures would usually exceed the limited number of redundant elements available for repair, and the entire memory device would be rendered unusable.
Consequently, a need exists in the art for container and stud structures that are not susceptible to falling problems during device fabrication and for a methodology for imparting such increased resistance to falling.
SUMMARY OF THE INVENTION
The present invention resolves the above and other problems that have been experienced in the art. More particularly, the present invention provides structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices. Although the concepts of this invention are particularly useful in DRAM fabrication, the invention nonetheless has wider applicability to encompass semiconductor devices in general where monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, need mechanical reinforcement against shear forces and the like that are experienced during processing and handling.
In one general embodiment, this invention concerns a monolithic semiconductor device comprising a semiconductor substrate over which are formed a plurality of upright free-standing microstructures. A brace layer is formed that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures. In order to form the braces, a dielectric layer is used as a sacrificial layer in which a narrow groove is formed and within which the brace layer is formed. Then, the sacrificial dielectric layer is removed after the brace is formed to leave a rel
Agarwal Vishnu K.
Sandhu Gurtej
Dickstein , Shapiro, Morin & Oshinsky, LLP
Fahmy Jr. Wael
Micro)n Technology, Inc.
Pham Hoai
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