Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-10-31
2003-12-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S586000, C438S673000
Reexamination Certificate
active
06656825
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of manufacturing integrated circuits, and, more particularly, to the formation of semiconductor devices including field effect transistors, resistors, capacitors and the like, wherein closely spaced individual circuit elements are connected by local interconnects.
2. Description of the Related Art
In steadily increasing the performance of integrated circuits and decreasing the size thereof, the individual circuit elements have continuously been reduced in size. Currently, critical feature sizes of 0.13 &mgr;m and beyond are accomplished. Besides steadily decreasing the feature sizes, it is, however, of great importance to provide for an efficient connection of the individual circuit elements to establish the required functionality of the circuit. Thus, the chip area required to manufacture a circuit primarily depends on the size of the required interconnect lines rather than on the dimensions of the circuit elements, such as transistors, resistors and the like. It is thus common practice to provide a plurality of overlying wiring levels, also referred to as metallization layers, in which trenches and vias, filled with an appropriate metal, provide for the required conductive connections, also referred to as interconnects. Since each additional metallization layer significantly contributes to process complexity, semiconductor manufacturers are steadily seeking for improvements in view of reducing the number of metallization layers required for interconnecting the semiconductor elements. Reducing the number of metallization layers, however, requires one to steadily reduce the dimension of the respective conductive lines and vias to save on chip area so as to allow the fabrication of a greater number of interconnects on a single metallization layer.
Generally, reducing the dimensions of the conductive lines and vias also results in an associated increase in the electrical resistance of the lines and vias. One approach to counteract this increase in resistance is to replace the frequently used metallization metal aluminum with copper, which exhibits a significantly lower resistance than aluminum. Further progress in increasing interconnect density has been made by the introduction of so-called local interconnects, wherein closely-spaced or adjacent individual elements may directly be connected without providing an interlayer dielectric that requires the formation of vias and trenches in the dielectric layer to connect these devices.
Several approaches have been proposed and are currently realized in forming local interconnects. However, a compromise between process complexity and functionality of the local interconnects usually has to be made. While, from a functional point of view, a highly conductive material is desirable, integration of an according metallization process has been proven to add an undue amount of process complexity. It has thus become a frequently preferred technique to provide local interconnects as polysilicon features that are formed together with gate electrodes of the field effect transistors so that these local interconnects and any polysilicon lines that may connect various chip areas exhibit substantially the same conductivity as the gate electrodes of the field effect transistors. Since these polysilicon lines and the local interconnects, although heavily doped, exhibit a relatively high electrical resistance, these circuit features may not be scaled down in the same manner as, for example, gate electrodes, since otherwise signal propagation delay would be restricted by local interconnects and polysilicon runners rather than by the transistor devices.
In other approaches, closely-spaced semiconductor regions, such as a gate electrode and a source or a drain region of the transistor, may be connected after the formation of the transistor device by depositing a refractory metal that is patterned by an appropriate local interconnect mask to provide for the desired connection. Although this approach offers highly conductive local interconnects compared to polysilicon-based interconnects, a plurality of additional process steps, such as a plurality of deposition and etch steps, is required, thereby adding to process complexity.
In view of the situation pointed out above, there exists a need for an improved technique for forming local interconnect structures providing for low resistivity while not unduly contributing to process complexity.
SUMMARY OF THE INVENTION
Generally, the present invention is directed to devices and methods in which the conventional sidewall spacer technique used for achieving a desired dopant profile in the drain and source regions of field effect transistors is modified in such a way that the sidewall spacers include a highly conductive layer that is separated from an underlying area by a dielectric layer. This highly conductive layer is also patterned to provide for the required local interconnect between closely-spaced features, for example, between a gate electrode and an adjacent active area, such as a drain or a source region of the same or an adjacent transistor element. Moreover, any device features that are patterned along with the gate electrodes of the field effect transistors, such as any polysilicon runners, will also receive the sidewall spacers including the highly conductive layer so that the electrical resistance of these polysilicon runners may be significantly reduced due to being shunted by the highly conductive spacer layer.
According to one illustrative embodiment of the present invention, a semiconductor device comprises a substrate having a semiconductor layer provided thereon, wherein the semiconductor layer includes a first active region and a second active region with the first and second active regions being separated by an insulating region. A semiconductor containing line is provided and has sidewalls and an upper surface, wherein the semiconductor containing line is located at least partially above the first active region. A dielectric layer is formed adjacent to the sidewalls of the semiconductor containing line and is in contact therewith. Moreover, the semiconductor device comprises a conductive layer formed adjacent to the dielectric layer and on a portion of the upper surface, wherein the conductive layer includes an interconnect extension portion formed partially on the insulating region and the second active region to form a local interconnect.
According to a further illustrative embodiment of the present invention, a semiconductor device comprises a substrate having a semiconductor layer provided thereon, wherein the semiconductor layer includes an active region and an insulating region. A first semiconductor containing line is located above the insulating region and has sidewalls and an upper surface. A second semiconductor containing line is located on the insulating region, spaced apart from the first semiconductor containing line and having sidewalls and an upper surface, wherein the first and second semiconductor containing lines each includes a dielectric layer formed on the respective sidewalls of the first and second semiconductor containing lines. The semiconductor device further comprises a conductive layer formed adjacent to the dielectric layer and on respective portions of the upper surfaces of the first and second semiconductor containing lines, wherein the conductive layer further includes an interconnect extension portion formed on the insulating region and connecting the first and second semiconductor containing lines.
According to a further embodiment of the present invention, a field effect transistor comprises a drain and a source region formed in an active region and a gate electrode formed over the active region and separated therefrom by a gate insulation layer, wherein the gate electrode has sidewalls and an upper surface. The field effect transistor further includes spacer elements formed adjacent to the sidewalls, wherein the spacer elements comprise a dielectric l
Advanced Micro Devices , Inc.
Pham Thanh V
Williams Morgan & Amerson P.C.
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