MROM memory cell structure for storing multi level bit...

Details MROM memory cell structure for storing multi level bit... MROM memory cell structure for storing multi level bit...

2002-05-24

2003-09-16

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C257S392000, C257S396000, C257S903000, C257S905000

Reexamination Certificate

active

06621129

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory devices, and more particularly to a MROM memory cell structure for storing multi level bit information.
2. Description of the Prior Art
There are several read-only memory (ROM) cell structures are well known in application. One approach is referred to as the flat-type ROM design. With the requirement of better memory cell efficiency, the cell pitch and bank height become the key factor to be considered. While the memory cell is shrinking down, the contact size and metal pitch become the limit of it. On the other hand, memory array used to use LOCOS-type MOS for the bank selection transistors, which causes difficulties in the reduction of the layout area.
In general, read-only-memories (hereinafter referred to as ROMS) are used for storing data information in a permanent, non-volatile form. Semiconductor ROMs find particular application in digital electronic equipment such as computers, office equipment, and game machines where they are used to store permanent data information. Such permanent data information includes control microprograms, electronic games, printer fonts, etc. With the continuing advances in digital electronics and the corresponding need for larger quantities of data information, the demand for cheaper and higher capacity ROMs is growing.
Semiconductor ROMs generally store their data information in arrays of memory cells, wherein each memory cell is a single transistor. The data bits held by the memory cell transistors are permanently stored in the physical or electrical properties of the individual memory cell transistors. For example, in a typical ROM wherein the memory cell transistors are MOSFETs (metal-oxide-semiconductor field effect transistors), memory cell transistors having a first threshold voltage store data bits of value “0” whereas memory cell transistors having a second threshold voltage different from the first threshold voltage store data bits of value “1”.
Semiconductor ROMs are generally formed by intersecting a plurality of bit lines, which have been diffused into a semiconductor substrate with a plurality of word lines lying over the substrate. The word lines are physically separated from the bit lines and the substrate by a thin gate oxide layer such that an array of memory cell MOSFET transistors is formed. In the array, the word lines serve as gates for the memory cell transistors while the bit lines serve as source and drain diffusion regions. Then, by properly adjusting the dopant concentrations of the channel regions of the individual memory cell transistors, the memory cell transistors are programmed to exhibit the threshold voltages corresponding to the data bits they store. In the case of mask-programmable read-only-memories (or, alternatively, mask ROMs or simply MROMs), the coding of the data bits onto the memory cell transistors is generally performed by implanting ions into the channel regions of the appropriate memory cell transistors, thereby adjusting their threshold voltages.
FIG. 1
illustrates a top view of the prior art of a semiconductor substrate under fabrication as a MROM memory device. The top view comprises a polysilicon layer
100
, a source region
102
, a drain region
104
, and a transistor
106
, wherein the transistor
106
is formed between the source region
102
and the drain region
104
. The transistor
106
serves as mask-read-only-memory cell. The transistor
106
is only used two types as “0” and “1”. The process window is too small and the channel length is the same in the conventional of MROM structure. The conventional of MROM structure for storing data states only have “0” and “1” types by applying a different voltage.
For the forgoing reasons, there is a necessity for a structure of a MROM memory cell structure for storing multi level bit information.
SUMMARY OF THE INVENTION
In accordance with the present invention is provided a MROM memory cell structure for storing multi level bit information that the invention is to form different channel length under the substrate of MROM by using at least two different photolithography steps. This invention transistor area is as same as conventional transistor area but memory array is more than conventional transistor. The process window is better than conventional transistor because this inventive structure is formed under the substrate.
In accordance with the present invention is provided a MROM memory cell structure for storing multi level bit information that the structure is formed under the substrate and the surface of transistors is flat so as to increase process window.
One object of the present invention is to provide a MROM memory cell structure for storing multi level bit information that the surface area of transistors is reduced so as to increase memory capacitance of memory array.
Another object of the present invention is to provide a MROM memory cell structure for storing multi level bit information that the different channel lengths are formed by using different trench depth.
Further another object of the present invention is to provide a MROM memory cell structure for storing multi level bit information that the data states more than “0” and “1” can be stored by using different channel lengths.
In order to achieve the above objects, the present invention is to provide a MROM memory cell structure for storing multi level bit information. First of all, a substrate is provided. The substrate has first and second trenches therein, wherein the first trench is deeper than second trench. A conformal dielectric layer formed on sidewall and bottom of the first and second trenches. A conductive layer filled in the first and second trenches and on the substrate. A first doped region is formed under the first trench. A second doped region is formed under the second trench. A third doped region is formed in surface of the substrate and between the first and second trenches.


REFERENCES:
patent: 4864374 (1989-09-01), Banerjee
patent: 4999811 (1991-03-01), Banerjee
patent: 5016071 (1991-05-01), Kumagai et al.
patent: 5710072 (1998-01-01), Krauntchneider et al.
patent: 6110773 (2000-08-01), Lee

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