Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-06-20
2003-09-30
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189090, C327S512000, C327S513000
Reexamination Certificate
active
06628558
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for voltage generators generally and, more particularly, to a method and/or architecture for a proportional to absolute temperature (PTAT) voltage generator.
BACKGROUND OF THE INVENTION
Data (e.g., a “1” or a “0”) is stored in a 1T memory cell as a voltage level. A “1” is stored as a high voltage level which can decrease due to leakage. A “0” is stored as a voltage level of zero volts which can increase due to leakage. The 1T memory cell requires a periodic refresh to maintain the voltage level stored in the cell. In many applications, a memory chip uses a ring oscillator to control when the refreshes occur. The frequency of a signal generated by a typical ring oscillator decreases with increasing temperature because of CMOS device characteristics. However, the memory cell leakage increases with temperature. As the temperature increases, refresh using a conventional oscillator can occur less frequently than necessary to maintain the voltage level stored in the memory cell. Thus, the oscillator needs to be designed to support the high temperature refresh rate at the expense of more current.
Proportional to absolute temperature(PTAT) voltages and currents are used in temperature monitoring circuits. The monitoring circuits either detect a specific temperature or output a voltage and/or current that increases with temperature. The temperature monitoring circuits can use a PTAT and an inverse PTAT, where the crossing point is a desired temperature. A conventional method of generating PTAT voltage is to use a delta Vbe generator circuit.
Referring to
FIG. 1
, a block diagram of a circuit
10
is shown. The circuit
10
is a delta Vbe generator circuit that can generate a PTAT voltage VREF. The voltage VREF is described by the following equation 1:
Vref
=
Vbe
1
=
n
·
k
q
·
ln
(
n
·
k
·
ln
(
B
)
·
T
q
·
A
·
Is
·
R
+
1
)
·
T
Eq
.
1
where T is the absolute temperature in Kelvin, n is the emission coefficient, k is Boltzmann's constant, q is the charge of an electron, Is is the theoretical reverse saturation current, A is the smaller of the areas of diodes
12
and
14
, B is the ratio of the areas of the diodes
12
and
14
, and R is the resistance of the resistor
16
. The resistance R generally has a positive temperature coefficient. The emission coefficient n is related to the doping profile and affects the exponential behavior of the diodes
12
and
14
. The value of n is normally approximated to be 1.
The voltage VREF is proportional to the temperature T, ln(T), and 1/R(T). Also, a current I is generated equal to Vt*ln(B)/R which is proportional to temperature since R has a positive temperature coefficient and Vt=k*T/q. The voltage VREF is generated by using a voltage across a diode with the bandgap current I flowing through the diode. The circuit
10
has the following disadvantages: a complex relationship between temperature and the voltage VREF (i.e., the voltage VREF is a function of T, ln(T), and ln(1/R(T)); the value of the voltage VREF is limited when the bandgap current I is also used to generate a PVT compensated voltage; and a larger value for the voltage VREF requires a higher current I.
SUMMARY OF THE INVENTION
The present invention concerns a biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.
The objects, features and advantages of the present invention include providing a method and/or architecture for a proportional to absolute temperature (PTAT) voltage generator that may (i) use a bandgap reference with a current equal to Vt*ln(B)/R, (ii) use one additional resistor to form a linear PTAT voltage reference, and/or (iii) provide a PTAT voltage reference that may be scaled by a ratio of resistor values.
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Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Miller Robert M.
Nguyen Van Thu
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