Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-01-25
2003-09-30
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S135000
Reexamination Certificate
active
06629268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to computer systems, and more specifically to a method and apparatus for servicing a processing system. In particular, the present invention makes use of a service processor that can access cache memory and control registers within a processor core by generating operations on an internal bus of one or more main processors.
2. Description of the Related Art
Modern computer systems have grown sufficiently complex that secondary service processors are used to provide initialization of the computer system, allowing synchronization of their many components and, in some cases, startup assistance to components that do not completely self-initialize. In today's multiprocessor computer systems, data values and instructions are preloaded, and out-of-order execution is supported, making the synchronization and reliability of the processing cores critical to proper operation.
Both multiprocessor and uniprocessor systems typically use multi-level cache memories where typically each higher level is smaller and has a shorter access time. The cache accessed by the main processor(s), and typically contained within the processor component of present systems, is typically has the least storage. Both data and instructions are cached, and data and instruction cache entries are typically loaded by prefetch units and branch prediction units before they are needed by an execution unit. At any time, these caches may contain values associated with multiple threads of execution and possibly multiple potential streams of execution loaded in accordance with predictions made by branch prediction and prefetch units. When an error occurs, resynchronizing the contents and coherence state of all of the caches in the system can be a complex tracing problem.
During initialization of a computer system, the service processor performs such tasks as controlling preloading cache memory and initializing of the individual processor cores before the cores are enabled for processing instructions. The service processor may also handle error events occurring in the system and may take a processor off-line if a fault has occurred or if the processor fails to initialize. Design trends in modem processor cores make use of this service processor increasingly prevalent, and the tasks which the service processor must perform are also increasing in number, due to the complexity of the memory hierarchy and the number of execution and control units within the core. The service processor helps to sequence proper startup by presetting control registers within the core, controlling the various execution and control units and presetting the arrangement of the memory hierarchy before the main processors are enabled to execute instructions.
As the speed of processors increases, the use of dynamic circuits and asynchronously timed interconnects force modern processing system designs toward fault tolerant operation.
The initialization and synchronization requirements of the processing systems also increase. Rather than removing a processor from a multiprocessing system, or restarting a processor, an approach geared toward dynamic fault recovery is needed. In addition, processing systems must be designed to handle certain fault rates, as opposed to past processing systems wherein a single fault usually required halting execution of a processor pending correction of the fault. Fault tolerance in the past has been directed at handling software faults, which occur due to the difficulty of handling all combinations of execution that might occur on one or more processors in a particular sequence of instructions. The new trends in circuit designs increase the need for tolerance of hardware faults, which have been corrected in the past by a hardware reset.
The need for a fault tolerant design methodology comes in part from the increasing demand for reliability and increasing processing speeds from consumers. One way to increase the rate at which a circuit can evaluate the next state in a computational engine is to permit an increase in the error rate for that evaluation.
An error in evaluation in processor control logic, however, can be fatal to execution in the core. Unlike a data error or an unpredicted program path, a control fault can create an unexpected next state from which there is no recovery. Also, it is difficult or impossible to evaluate all of the possible next state conditions due to errors. Even if the error rates are very low, an error occurring at low frequency (even on the order of days) must be either avoided or made recoverable.
Present computer systems, when faced with a core error, can reset the core. For a multiprocessor system, this is not a simple operation, as the interdependencies of memory values based on cache storage raise the potential to corrupt computations being performed on the entire machine. An individual execution unit may have an associated cache containing values that have been modified, but not flushed to a lower level of the memory hierarchy accessible to other execution units. These values are marked as “dirty” in the other levels of the hierarchy, and can cause halting in other execution units which require the values, until the values are replaced. If the values were held in a cache associated with an execution unit which faulted, it may be necessary to restart the entire machine, or restart all of the software processes executing on the machine. Even in a uniprocessor system, multithreading operation can make cache synchronization after an execution fault a difficult or impossible task.
In light of the foregoing, it would be desirable to provide an improved service processor and a method of managing processing systems that allows enhanced fault detection and fault handling in uniprocessor and multiprocessor systems.
SUMMARY OF THE INVENTION
The above objectives are achieved in a method and apparatus for servicing a processing system component through a test port, including an interface means coupled to the test port for generating a transaction on a bus internal to the processing system component when the test port receives at least one state control command for setting the state of the internal bus.
Alternatively, apparatus may include service logic means which determines if a command is a transaction command and the interface means may generate the transaction directly. The interface further returns results of a transaction when the test port receives a read result command for reading a result of the transaction. The test port used may be a JTAG interface and may also include an attention signal coupled from the processing system component to the service processor for alerting the service processor that the processing system component needs attention. The attention signal may be made physically larger for reliability. The interface means may coherently access cache or flush cache inside or outside the main processor, by virtue of the fact that the bus cycles are generated in consonance with the operation of the internal bus. Memory, cache, or control registers in other processors may be accessed by the interface, since any memory mapped component in the system can be accessed if it has a flat address in global memory space.
Accessing a location outside of the processing system component will cause a bus interface within the processing system component to generate an external bus cycle on a bus to which the processor is coupled, in order to access external devices. Cache flush operations may be performed by generating read-with-intent-to-modify cycles addressing cache locations, which will cause the cache controller to mark the locations as “dirty”.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5561761 (1996-10-01), Hicok et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5649090 (1997-07-01), Edwards et al.
patent: 6055656 (2000-04-01), Wilson et al.
patent: 6115
Arimilli Ravi Kumar
Reick Kevin F.
Beausoliel Robert
Bracewell & Patterson L.L.P.
Duncan Marc
Slays Casimer K.
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