Ion beam dual damascene process

Details Ion beam dual damascene process Ion beam dual damascene process

2001-09-14

2003-09-16

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S639000, C438S524000

Reexamination Certificate

active

06620729

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit fabrication. More particularly the invention relates to forming vias in integrated circuit structures as part of a dual-damascene fabrication process.
BACKGROUND
Increasingly, dual-damascene processing is being used to form copper interconnects in semiconductor circuits. Generally, there are two types of dual-damascene processes: trench-first and via-first. In via-first processing, a via cavity is etched completely down to an underlying conductor, and is then filled with material to protect the via cavity during a subsequent trench etch process. In trench-first processing, the trench is patterned and etched first, and then the via cavity is patterned and etched within the trench.
Trench-first processing has had several drawbacks, including difficulty in aligning and etching the via cavity within the trench. The alignment problem is exacerbated by the slope which is usually present in the sidewalls of a via cavity formed according to a traditional etching process.
What is needed, therefore, is a more directional process for forming a via cavity in a trench-first dual-damascene process, thereby improving the alignment of the via cavity with an underlying conductor.
SUMMARY
The above and other needs are met by a process for forming an integrated circuit structure. The process includes forming a trench in a dielectric substrate, and forming a via mask layer over the dielectric substrate and the trench. An aperture is formed in the via mask layer overlying the trench, thereby exposing a portion of the underlying dielectric substrate. The process includes subjecting the exposed portion of the dielectric substrate to an ion beam to damage the exposed dielectric material. The portion of the dielectric substrate that was subjected to the ion beam is then removed, such as by etching, thereby forming a via cavity in the dielectric substrate.
Generally, the damaged portions of the dielectric substrate etch at a faster rate than do adjacent non-damaged regions. With a faster etch, there is practically no outward spreading of the via cavity as the etch proceeds downward through the dielectric substrate, thereby forming a via cavity wall that is very nearly vertical. More precise control of via cavity geometry provides for more precise alignment of the via cavity with underlying conductors in the integrated circuit structure.
In various preferred embodiments, after removing the via mask layer, metal is deposited over the dielectric substrate, thereby substantially filling the via cavity and the trench with the metal. The metal is then selectively removed from the dielectric substrate, such as by planarization, while leaving the metal in the trench and the via cavity.


REFERENCES:
patent: 5933761 (1999-08-01), Lee
patent: 6080663 (2000-06-01), Chen et al.
patent: 6171951 (2001-01-01), Lee et al.
patent: 6287961 (2001-09-01), Liu et al.
patent: 6326300 (2001-12-01), Liu et al.

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