Semiconductor memory device having a bit line constituted by a s

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257296, 257302, H01L 2978

Patent

active

052763439

ABSTRACT:
A DRAM cell having a bit line constituted by a semiconductor layer. The DRAM cell comprises a semiconductor substrate of a first conductivity type having a main surface, an insulating film formed on the main surface, an opening formed in the insulating film to communicate with the substrate, and a bit line formed by a semiconductor layer of a second conductivity type formed on the insulating film and that portion of the substrate which is exposed through the opening.

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patent: 4829017 (1989-05-01), Malhi
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4914739 (1990-04-01), Malhi
patent: 4974060 (1990-11-01), Ogasawara
IBM Technical Disclosure Bulletin, vol. 23, No. 9, pp. 4052-4053, published Feb., 1981, Kenny, "Reduced Bit Line Capacitance in VDMOS Devices".
IEDM Technical Digest., p. 714 (1985), W. F. Richardson, et al "A Trench Transistor Cross-Point Dram Cell".
IEDM Technical Digest., p. 39 (1989), T. E. Tang. "In-Situ Doped Polysilicon Using Vapor Dorant for High Density DRAMs".

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