Semiconductor memory

Details Semiconductor memory Semiconductor memory

2001-05-02

2003-09-30

Everhart, Caridad (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S393000, C257S402000, C257S406000, C257S410000, C257S411000, C257S392000

Reexamination Certificate

active

06627962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and its manufacturing method; and more particularly to a semiconductor memory and its manufacturing method in which it is possible to manufacture high-integrated semiconductor memory in spite of its size of memory cells.
2. Description of Related Art
Conventionally, as for the semiconductor memory, there is the mask-ROM (Mask Programmed Read Only Memory). With reference to the mask-ROM, writing of data is carried out during the manufacturing process thereof. However, the mask-ROM is subjected to diffusion process of ion in which ion implantation is carried out in order to inject impurity into silicon substrate by the use of ion such as boron and so forth. In the diffusion process of the ion, the writing of data is carried out depending on this ion injection. Diffusion of the ion occurs in the lateral direction caused by this ion injection. Thus, there is malfunction that interference occurs between neighboring memory cells caused by the diffusion of the ion in the lateral direction. Specifically, the diffusion of the ion in the lateral direction causes threshold voltage to increase of the ON-bit memory cell neighboring the OFF-bit memory cell, thus, there is malfunction that ON-bit memory cell is rewritten into the OFF-bit memory cell caused by increase of the threshold voltage of the ON-bit memory cell. For that reason, the memory cell has a limit in connection with its miniaturization. For instance, it is difficult to form the microscopic memory cell not more than 0.20 &mgr;m. Further, since the writing of data to the mask-ROM is carried out at the diffusion process, there is malfunction that many various intermediate off-the-shelf products according to content of the writing of data should be held by the time the manufacturing process ends.
Accordingly, OTP (One Time Programmable Read Only Memory) is employed as the measure for overcoming aforementioned malfunction. This OTP is PROM (Programmable Read Only Memory) to which writing data of only one time is capable of being carried out. The writing of data is carried out electrically. Therefore, interference between neighboring memory cells such as aforementioned mask-ROM can be inhibited. Since, it is only necessary to ensure reliability of writing of data of one time, it is possible to manufacture of the OTP cheaper than general semiconductor memory such as PROM, flash memory and so forth. Further, the OTP is capable of being written of the data after completion of the manufacturing process of the semiconductor memory not the process of diffusion of the ion (for instance in the test process), accordingly, inventory control becomes easy in comparison with the aforementioned mask-ROM.
Here, as for the OTP, which is explained on the basis of
FIG. 4
, FIG.
5
and FIG.
6
.
FIG. 4
shows top plan typical view of memory cell portion of Virtual Ground Cell type large capacity NOR type OTP (semiconductor memory)
120
having impurity diffusion region
106
as a digit line. Further,
FIG. 6
is a view illustrating a manufacturing process of this OTP
120
as well as a sectional view illustrating an arrow A—A of FIG.
4
.
The OTP
120
, as illustrated in
FIG. 5
, has a p-type silicon substrate
101
as single crystal silicon substrate, an impurity diffusion region
106
formed on the surface of this p-type silicon substrate
101
, and a gate insulator
107
made of silicon oxide film that is formed on the surface of this p-type silicon substrate
101
. Further, the OTP
120
has a floating gate electrode
109
made of polycrystalline silicon film formed on the gate insulator
107
extending between neighboring impurity diffusion regions
106
, interelectrode insulating film
110
formed at unevenness portion (unevenness portion consisting of the gate insulator
107
and the floating gate electrode
109
) of the p-type silicon substrate
101
, control gate electrode
111
made of polycrystalline silicon film for embedding this unevenness portion, and tungsten silicide (Wsi) film
112
which is deposited on the control gate electrode
111
.
Continuously, about manufacturing method of the OTP
120
is explained.
In the OTP
120
, as illustrated in FIG.
6
(
a
), firstly, buffer layer
102
made of oxide film is formed on the surface of the p-type silicon substrate
101
by thermal oxidation of the p-type silicon substrate
101
, then, silicon nitride film
103
is deposited on the buffer layer
102
as insulating film. Then, the silicon nitride film
103
of a section that becomes impurity diffusion region
106
in the future is removed by photolithography and dry etching. After that, n-type injection layer
104
is formed in such a way that arsenic ion (As
+
) as n-type impurity is injected with the silicon nitride film
103
as mask material.
Continuously, as illustrated in FIG.
6
(
b
), the buffer layer
102
and the silicon nitride film
103
are removed. The gate insulator
107
is formed on the surface of the p-type silicon substrate
101
in such a way as to carry out thermal oxidation of this p-type silicon substrate
101
. Further, impurity diffusion region
106
is formed in such a way as to diffuse impurity of the n-type injection layer
104
during heat treatment carried out after such thermal oxidation. Furthermore, polycrystalline silicon film
108
is deposited on the gate insulator
107
. Then, as illustrated in FIG.
6
(
c
), floating gate electrode
109
made of the polycrystalline silicon film
108
is formed in such a way that the polycrystalline silicon film
108
on the impurity diffusion region
106
is subjected to patterning.
For instance, the floating gate electrode
109
is formed by the photolithography. On this occasion, the patterning is made to carry out while being employed approximately rectangular mask pattern for processing the floating gate electrode
109
.
Subsequently, as illustrated in FIG.
6
(
d
), an interelectrode insulating film
110
is formed on unevenness portion (unevenness portion consisting of the gate insulator
107
and the floating gate electrode
109
) of the p-type silicon substrate
101
. After that, the unevenness portion is embedded by the polycrystalline silicon film. Thus, the control gate electrode
111
made of the polycrystalline silicon film is formed. Further, tungsten silicide (WSi) film
112
which is deposited due to chemical vapor deposition method (CVD method) on the control gate electrode
111
is formed.
After that, as illustrated in
FIG. 4
, the OTP
120
is formed in such a way that patterning is made to carry out while leaving the floating gate electrode
109
that becomes word line
114
, the interelectrode insulating film
110
, the control gate electrode
111
and the tungsten silicide (WSi) film
112
.
The OTP
120
indicated in the aforementioned conventional example has capacitance “Csub” between the p-type silicon substrate (except impurity diffusion region
106
) and the floating gate electrode
109
as well as capacitance “Cg” between the floating gate electrode
109
and the control gate electrode
111
. Further, if one side of the impurity diffusion region
106
is taken to be drain region, while the other side is taken to be source region, the OTP
120
has capacitance “Cd” between the drain region and the floating gate electrode
109
, as well as capacitance “Cs” between the source region and the floating gate electrode
109
.
Ratio of the capacitance “Cg” between the floating gate electrode
109
and the control gate electrode
111
relative to the total capacitance of all is called as capacitive coupling ratio “Cr”, and this capacitive coupling ratio “Cr” is indicated by formula (1):
Cr=Cg
/(
Cg+Csub+Cd+Cs
)  (1)
One capacitance is mutual capacitance in the portion that the floating gate electrode
109
is extended over the impurity diffusion region
106
(capacitance “Cd” between the drain region and the floating gate electrode
109
as well as capacitance “Cs” between the source region and the f

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