Cell data protection circuit in semiconductor memory device...

Details Cell data protection circuit in semiconductor memory device... Cell data protection circuit in semiconductor memory device...

2001-12-31

2003-04-01

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000, C365S203000

Reexamination Certificate

active

06542426

ABSTRACT:

BACKGROUND
1. Field of Invention
The inventions described in this patent document relate in general to cell data protection for a semiconductor memory device and methods of driving a dynamic random access memory (DRAM) during refresh mode to protect cell data during a refresh mode operation.
2. General Background and Related Art
A general construction of a DRAM is explained with reference to
FIG. 1
(Prior Art) to provide appropriate background and context for the description of the claimed inventions. A DRAM includes a memory cell array part
10
storing a plurality of data, a row address buffer part
11
receiving an m bit row address A
0
~Am−1, a column address buffer part
12
receiving an n bit column address A
0
~An−1, a row decoder part
13
selecting a word line(s) (not shown in the drawing) of the memory cell array part
10
by a signal outputted from the row address buffer part
11
, a column decoder part
14
selecting a bit line(s) (not shown in the drawing) of the memory cell array part
10
by a signal outputted from the column address buffer part
12
, a data input buffer part
15
receiving data, and an output buffer part
16
outputting data DQ
0
~DQ
K
−1. The DRAM further includes a sense amplifier part
17
connected to the bit line(s) in the memory cell array and amplifying a data signal(s) read from the selected cell(s), an I/O gate circuit part
18
responding to an output(s) of the column decoder part
14
and connecting the bit line(s) in the memory cell array selectively to the data input and output buffer parts
15
and
16
, and a chip control part
20
controlling operations of peripheral circuits of the memory cell array part
10
.
As is well known, each of the memory cells in DRAM includes a selection transistor and a data storage capacitor. Thus, DRAM is widely used as a semiconductor memory device proper for increasing the integration density on a semiconductor substrate.
Yet, electric charges leak through the storage capacitor and selection transistor in DRAM. Thus, it is necessary to refresh by recharging the DRAM memory cells with electric charges periodically. Compared to SRAM or non-volatile semiconductor memory, DRAM, as shown in
FIG. 1
(Prior Art), further includes a refresh circuit part
30
enabling data signals stored in the memory cells to be amplified by the sense amplifier part
17
periodically so as to be re-written in the memory cells. The refresh circuit part
30
is constructed with a refresh timer part
31
producing timing a signal(s) for carrying out a periodic refresh operation, a refresh control part controlling overall operations relating to the refresh in a memory device in accordance with the timing signal(s), and a refresh address producing part
33
producing internal refresh addresses by being controlled by the refresh control part
32
.
There are well-known methods for refreshing DRAM cells. Common refresh methods are explained in brief as follows.
First, RAS Only Refresh (ROR) is a method of refreshing cells by activating a row address strobe bar (/RAS) only while a column address strobe bar (/CAS) signal maintains a precharge level. In ROR, a memory device should be provided with refresh addresses from outside for the respective refresh operations. Address buses connected to the memory device fail to be used for other purposes during the respective refresh operations.
Second, there is CAS-Before-RAS (CBR) refresh. Such a CBR refresh is carried out by producing row addresses in the refresh timer part
31
built in a DRAM chip instead of giving refresh addresses from outside.
Third, there is Hidden Refresh as another refresh method. In Hidden Refresh, a read operation is combined with a CBR operation. During a read cycle, when /CAS becomes active as ‘low’, output data maintains still valid. In this case, if /RAS becomes ‘high’ and then returns to ‘low’, a CBR state begins. Thus, one cycle of the CBR refresh is completed. As data output part
16
is controlled by /CAS only, it seems externally that valid data are outputted during this cycle all the time so as to be a normal read operation. Yet, the refresh is internally performed using internal addresses produced by a CBR counter. Therefore, it is called Hidden Refresh.
In the above-explained ROR, CBR refresh, and Hidden Refresh, the /RAS signal is applied thereto from outside and refresh addresses are received from outside or produced internally, which is so-called a pulse refresh method. Lately, the /RAS signal used as a refresh synchronizing signal is also used for the purposes such as low power consumption on an operation mode produced inside DRAM, battery back-up (BBU) and the like. Namely, only if DRAM control signals satisfy a specific timing condition (in this case, at least 100 elapses by maintaining this mode after CBR is entered) (i.e. if a self-refresh pulse width tRASS is at least 100, a refresh demanding signal is produced automatically by the refresh timer part
31
without the external control signal so that the RAS series control signals are produced automatically inside the device and the refresh operation is executed by the address generated inside. Such a refresh operation is called Self-Refresh.
The self-refresh mode is used for a low power consumption operation or a long-term data storage. In the self-refresh mode, entire input pins including clocks except a clock enabling cke pin become inactive and a refresh enter command and the refresh addresses are generated to extend their periods, thereby enabling to reduce the power consumption.
The self-refresh mode, when the entire banks are at an idle state, is entered by making a chip selection signal /CS, a RAS bar signal /RAS, a CAS bar signal /CAS, and a clock enabling signal CKE become ‘low’ and a write enabling signal /WE become ‘high. Once this mode is entered, all the input pins except the clock enabling cke signal are ignored.
A method of escaping from the self-refresh mode includes the following steps. First, a clock buffer is normalized by inputting a clock normally thereto and making the clock enabling signal cke become ‘high’ . After a predetermined time (/RAS precharge time) tRP elapses, SDRAM becomes at an idle state. It is then able to input another command thereto at this state.
A time interval required for refreshing all the rows on a cell array, i.e. a time length from a refresh operation of a certain row in a memory cell array to another refresh operation of the next row, is generally called a refresh period. For instance, in 16 MB DRAM carrying out 2K(2048) refresh cycles per a period and constructed with 2048 rows×512 columns×16 bits, when a maximum time interval, i.e. a refresh cycle, required for refreshing 512 memory cells connected in a row is 128 ms, it is necessary to refresh 2048 rows in order within the time interval. In such a case, an inter-cycle time interval, i.e. a refresh clock period, becomes about 62.5 (=128÷2048 rows) and one refresh cycle, ex. 80 to 200 ns, is executed per given time interval of 62.5.
FIG. 2
(Prior Art) is a timing diagram explaining a read-modify-write (RMW) operation in a general DRAM. The same data having been read from a selected memory cell are written in the same memory cell which is meaning less. Hence, the data having been read are written reversibly (i.e. modified) in the memory cell in the read-modify-write (RMW) operation,
‘tRWC’ is a read-modify-write cycle time during which ‘/RAS’ becomes active as ‘low’. And, ‘tRP’ is a /RAS precharge time for an interval during which ‘/RAS’ having become active as ‘low’ is precharged as ‘high’. ‘tRWD is a time interval from a time point at which a ‘/RAS’ becomes active low to another time point at which ‘/WE’ becomes active as ‘low’. ‘tRWL’ is an time interval from a time point at which a write enabling bar signal /WE becomes active as ‘low’ to another time-point at which ‘/RAS’ becomes active as ‘low’. ‘tCWL’ is an time interval from a time point at which the write enabling bar signal /WE becomes active as ‘low’ to another time point at which ‘/CAS

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