Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-20
2003-08-26
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S335000, C257S327000, C257S288000, C257S213000, C257S339000, C257S341000
Reexamination Certificate
active
06611021
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor structure applicable to semiconductor devices, such as a MOSFET (an insulated gate field effect transistor), an IGBT (an insulated gate bipolar transistor), a bipolar transistor and a diode, which simultaneously exhibit a high breakdown voltage and a high current capacity. More specifically, the present invention relates to a semiconductor device structure including a vertical drain drift layer and the method of manufacturing the semiconductor device.
BACKGROUND ART
The semiconductor devices may be roughly classified into a lateral device, that arranges the main electrodes thereof on one major surface, and a vertical device that distributes the main electrodes thereof on two major surfaces facing opposite to each other. In the vertical device, a drift current flows in the ON-state of the device and depletion layers expand in the OFF-state of the device both in the thickness direction of the substrate thereof (vertically).
FIG. 9
is a cross sectional view of a conventional planar-type vertical n-channel MOSFET. Referring now to
FIG. 9
, the vertical MOSFET includes an n
+
-type drain layer
11
with low electrical resistance; a drain electrode
18
in electrical contact with the back surface of n
+
-type drain layer
11
; a highly resistive n-type drain drift layer
12
on n
+
-type drain layer
11
; p-type base regions
13
(p-type well regions or channel diffusion regions) formed selectively in the surface portion of drain drift layer
12
; a heavily doped n
+
-type source region
14
formed selectively in the surface portion of p-type base region
13
; a heavily doped p
+
-type contact region
19
formed selectively in the surface portion of p-type base region
13
; a gate insulation film
15
on the extended portion of p-type base region
13
extended between-type drain drift layer
12
and n
+
-type source region
14
; a polysilicon gate electrode layer
16
on gate insulation film
15
; and a source electrode
17
in common contact with n
+
-type source region
14
and p
+
-type contact region
19
.
Highly resistive n-type drain drift layer
12
provides a vertical drift current path in the ON-state of the MOSFET and is depleted in the OFF-state of the MOSFET to increase the breakdown voltage. Shortening the current path in n-type drain drift layer
12
is effective to substantially reduce the on-resistance (the resistance between the source and the drain) of the MOSFET, Since the drift resistance is reduced. However, the shortening the current path in n-type drain drift layer
12
narrows the expansion width of the depletion layer expanding from the pn-junction between p-type base region
13
and n-type drain drift layer
12
. Since the depletion electric field strength soon reaches the maximum electric field (critical electric field) of silicon due to the narrowed expansion width of the depletion layer, the breakdown voltage (the voltage between the drain and the source) of the MOSFET is reduced. Although a high breakdown voltage is obtained by thickening n-type drain drift layer
12
, thick n-type drain drift layer
12
inevitably causes on-resistance increase, that further causes on-loss increase. In other words, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage. The tradeoff relation between the on-resistance and the breakdown voltage exists also in the other semiconductor devices such as IGBT's, bipolar transistors and diodes.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, Japanese Unexamined Laid pen Patent Application H09-266311 and Japanese Unexamined Laid Open Patent Application H10-223896 disclose semiconductor devices, which include an alternating conductivity type layer formed of heavily doped n-type regions and heavily doped p-type regions alternately arranged with each other to obviate the problems described above.
FIG. 10
is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. The vertical MOSFET of
FIG. 10
is different from the vertical MOSFET of
FIG. 9
in that the vertical MOSFET of
FIG. 10
includes a drain drift layer
22
, that is not of one conductivity type but of alternating conductivity types and formed of n-type drift current path regions
22
a
and p-type partition regions
22
b
alternately arranged with each other. Even if the impurity concentrations in the alternating conductivity type layer are high, a high breakdown voltage will be obtained, since depletion layers expand laterally, in the OFF-state of the device, from multiple pn-junctions extending vertically across the alternating conductivity type layer.
Drain drift layer
22
is formed in the following way. An n-type layer is grown epitaxially on an n
+
-type drain layer
11
as a substrate. Trenches are dug through n-type layer down to n
+
-type drain layer
11
, leaving n-type drift current path regions
22
a
. Then, p-type partition regions
22
b
are epitaxially grown selectively in the trenches. Hereinafter, the semiconductor device including a drain drift layer of alternating conductivity types as described above will be referred to sometimes as the “super-junction semiconductor device”.
Detailed dimensions of the super-junction semiconductor device disclosed in U.S. Pat. No. 5,216,275 are as follows. The thickness of drain drift layer
22
is described with a breakdown voltage V
B
by 0.024V
B
1.2
(&mgr;m). When the thickness of n-type drift current path regions
22
a
and the thickness of p-type partition region
22
b
are the same b and the impurity concentrations in n-type drift current path regions
22
a
and p-type partition region
22
b
are the same N, the impurity concentration and the thickness b are related with each other by N=7.2×10
16
V
B
0.2
b (cm
3
). When V
B
is 800 V and b is 5 &mgr;m, the impurity concentration N is 1.9×10
16
cm
3
. Since the impurity concentration in the conventional drain drift layer of one conductivity type is around 2×10
14
cm
3
, the drain drift layer of alternating conductivity types facilitates realizing a high impurity concentration therein, reducing the on-resistance and providing the semiconductor device with a high breakdown voltage.
However, the trenches for forming p-type partition regions
22
b
are narrow and deep. It is difficult for the presently available selective etching techniques to dig the trenches with such a large aspect ratio, and it is difficult for the presently available epitaxial growth techniques to grow a high-quality single crystal layer in such a narrow and deep trench. Since it is required to further narrow and thicken each region in the drain drift layer of alternating conductivity types to obtain a higher breakdown voltage, the aspect ratio of the trenches for forming the p-type partition regions should inevitably be larger. Obviously, the use of trenches for forming the p-type partition regions causes a limit for obtaining a higher breakdown voltage and, therefore, is not so practical.
In view of the foregoing, it is an object of the invention to provide a semiconductor device including a improved drain drift layer structure of alternating conductivity types, that is easy to manufacture. It is another object of the invention to provide a semiconductor device that facilitates realizing a high current capacity and a high breakdown voltage. It is still another object of the invention to provide a method of manufacturing the semiconductor device.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor device including: an alternating conductivity type layer formed of vertical first regions of a first conductivity type and vertical second regions of a second conductivity type; the vertical first regions and the vertical second regions being alternately arranged with each other; each of the vertical first regions or each of the vertical second regions being formed of epitaxially grown la
Fujihira Tatsuhiko
Iwamoto Susumu
Onishi Yasuhiko
Sato Takahiro
Flynn Nathan J.
Fuji Electric & Co., Ltd.
Mondt Johannes P
Rossi & Associates
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