Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-07-25
2003-12-16
Sparks, Donald (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S151000, C711S153000, C711S163000, C711S167000, C711S173000, C710S040000, C710S200000
Reexamination Certificate
active
06665777
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of computer systems. More particularly, the invention relates to computer systems where one or more central processing units (CPUs) are connected to one or more memory (RAM) subsystems, or portions thereof.
2. Discussion of the Related Art
In a typical computing system, every CPU can access all of the RAM, either directly with Load and Store instructions, or indirectly, such as with a message passing scheme.
When more than one CPU can access for manage the RAM subsystem or a portion thereof, certain accesses to that RAM, specifically allocation and deallocation of RAM for use by the Operating System or some application, must be synchronized to ensure mutually exclusive access to those data structures tracking memory allocation and deallocation by no more than one CPU at a time.
This technology, in turn, generates contention for those data structures by multiple CPUs and thereby reduces overall system performance. What is required is a solution that increases system performance by reducing contention for those data structures by multiple CPUs.
Heretofore, the requirements of reducing contention for those data structures by multiple CPUs and increasing system performance referred to above have not been fully met. What is needed is a solution that addresses these requirements.
SUMMARY OF THE INVENTION
There is a need for the following embodiments. Of course, the invention is not limited to these embodiments.
According to a first aspect of the invention, a method comprises: partitioning a block of memory into a plurality of shared memory segments; and providing a processor with accessibility to each of the plurality of shared memory segments. According to a second aspect of the invention, an apparatus comprises: a computer system; a block of memory including a plurality of shared memory segments; and a processor.
These, and other, embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating various embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many substitutions, modifications, additions and/or rearrangements may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such substitutions, modifications, additions and/or rearrangements.
REFERENCES:
patent: 4486834 (1984-12-01), Kobayashi et al.
patent: 5566321 (1996-10-01), Pase et al.
patent: 5568609 (1996-10-01), Sugiyama et al.
patent: 5604882 (1997-02-01), Hoover et al.
patent: 5737509 (1998-04-01), Fushimi et al.
patent: 5765157 (1998-06-01), Lindholm et al.
patent: 5946710 (1999-08-01), Bauman et al.
patent: 6026401 (2000-02-01), Brealey et al.
patent: 6026474 (2000-02-01), Carter et al.
patent: 6070194 (2000-05-01), Yu et al.
patent: 6125401 (2000-09-01), Huras et al.
patent: 6157989 (2000-12-01), Collins et al.
patent: 6360303 (2002-03-01), Wisler et al.
patent: 6427195 (2002-07-01), McGowen et al.
patent: 2003/0061395 (2003-03-01), Kinsbury et al.
patent: 0 602 791 (1994-06-01), None
patent: 0 917 056 (1999-05-01), None
patent: WO99/17196 (1999-04-01), None
patent: WO00/36509 (2000-06-01), None
International Search Report dated Jul. 16, 2002.
International Search Report dated Jun. 5, 2002.
Bershad, et al., “The Midway Distributed Shared Memory System” Compcon Digest of Papers, pp. 528-537, Feb. 22, 1993.
Wilson, et al. “Hardware Assist for Distributed Shared Memory” Proceedings of the International Conference on Distributed Computing Systems, pp. 246-255, May 25, 1993.
Songnian, et al. “Heterogeneous Distributed Shared Memory,” IEEE Transactions on Parallel and Distributed Systems, vol. 3, No. 5, pp. 540-554, Sep. 1, 1992.
Nitzbert, et al. “Distributed Shared Memory: A Survey of Issues and Algorithms,” IEEE Computer Society, pp. 52-60, Aug. 1, 1991.
Stumm, et al. “Algorithms Implementing Distributed Shared Memory,” IEEE Computer Society, pp. 54-64, May 1, 1990.
Ananthanarayanan, et al. “Experiences in Integrating Distributed Shared Memory with Virtual Memory Management,” Operating Systems Review, vol. 26, No. 3, pp. 4-26, Jul. 1, 1992.
Bisiani, et al., “PLUS: A Distributed Shared-Memory System,” Proceedings of the Annual International Symposium on Computer Architecture, pp. 115-124, May 28, 1990.
Levelt, “A Comparison of Two Paradigms for Distributed Shared Memory,” Software Practice & Experience, vol. 22, No. 11, pp. 985-1010, Nov. 1, 1992.
Ramachandran, et al. “Programming with Distributed Shared Memory,” Proceedings of the Annual International Computer Software and Applications Conference, vol. Conf. 13, pp. 176-183, Sep. 20, 1989.
Liviu Iftode et al., “Scope Consistency: A Bridge between Release Consistency and Entry Consistency,” Symposium on Parallel Algorithms and Architectures, New York, IEEE, US, vol. SYMP. 8, Jun. 24, 1996, pp. 277-287.
Cattaneo, “Another C Threads Library,” ACM Sigplan Notices, Association for Computing Machinery, New York, US, vol. 27, No. 12, Dec. 1, 1992, pp. 81-90.
Bolosky et al., “Simple but Effective Techniques for NUMA Memory Management,” Operating Systems Review (SIGOPS), ACM Headquarter, New York, vol. 23, No. 5, 1989, pp. 19-31.
International Search Report dated Apr. 23, 2002.
International Search Report for PCT/US02/23171 dated Mar. 3, 2003.
Song Jasmine
Sparks Donald
TNS Holdings, Inc.
LandOfFree
Method, apparatus, network, and kit for multiple block... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, apparatus, network, and kit for multiple block..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, apparatus, network, and kit for multiple block... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3096478