Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2002-09-10
2003-12-02
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S713000
Reexamination Certificate
active
06657295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilayer interconnect board and a multilayer semiconductor device, more particularly relates to a multilayer interconnect board comprised of a plurality of stacked cloth-reinforced resin layers and having at least one layer of an interconnect pattern formed at a stacking interface of the resin layers and to a multilayer semiconductor device using that multilayer interconnect board.
2. Description of the Related Art
A conventional multilayer semiconductor device comprised of a stacked plurality of resin layers is shown in FIG.
7
. The multilayer semiconductor device
100
is comprised of a multilayer interconnect board A on which a semiconductor chip
112
is carried. The multilayer interconnect board A is formed of three resin layers
104
a
,
104
b
, and
104
c
reinforced by glass cloth
102
as a reinforcing material and is formed with interconnect patterns
106
a
and
106
b
at the stacking interface X between the resin layer
104
a
and resin layer
104
b
and the stacking interface Y between the resin layer
104
b
and resin layer
104
c.
The resin layer
104
a
of the bottommost layer of the multilayer interconnect board A has lands
110
formed on its bottom surface for bonding with solder balls
202
provided as external connection terminals on a motherboard
200
.
The top surface of the topmost resin layer
104
c
of the interconnect board A carries the semiconductor chip
112
and is formed with bonding parts
116
. The semiconductor chip
112
and bonding parts
116
are electrically connected by wires
114
.
The bonding parts
116
on the top surface of the topmost resin layer
104
c
and the lands
110
on the bottom surface of the bottommost resin layer
104
a
are electrically connected through the interconnect pattern
118
formed on the top surface of the topmost resin layer
104
c
, vias
120
passing through the three resin layers
104
a
,
104
b
, and
104
c
, and an interconnect pattern
122
formed on the bottom surface of the bottommost resin layer
104
a
. Parts of the interconnect patterns
106
a
and
106
b
at the stacking interfaces are electrically connected to the vias
120
.
The semiconductor chip
112
and wires
114
carried on the top surface of the topmost resin layer
104
c
are sealed by a sealing resin
130
.
When the multilayer semiconductor device
100
is exposed to a thermal cycle in the state mounted on the motherboard
200
(large temperature rise or temperature fall cycle or small temperature rise/temperature fall cycle repeated), the heat stress occurring due to the difference in heat expansion coefficients between the multilayer semiconductor device
100
and the motherboard
200
is received by the solder balls
202
. This stress acts on the bonding interface between the solder balls
202
and the lands
110
and sometimes causes cracks
300
from the vicinity of the lands
110
in the bottommost resin layer
104
a.
The cracks
300
further advance in the bottommost resin layer
104
a
and sometimes cut the interconnect pattern
106
a
formed at the stacking interface X between the bottommost resin layer
104
a
and the directly higher resin layer
104
b
to cause electrical defects.
The occurrence of cracks
300
arising due to the heat stress is extremely difficult to prevent so long as there is a difference in heat expansion coefficients between the multilayer semiconductor device
100
and the motherboard
200
. It is also extremely difficult to eliminate the above difference in heat expansion coefficients.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a multilayer interconnect board and a multilayer semiconductor device not suffering from electrical defects due to disconnection of interconnect patterns due to cracks occurring from nearby lands of a bottommost resin layer of a multilayer semiconductor device when a multilayer semiconductor device using a multilayer interconnect board comprised of a plurality of stacked cloth-reinforced resin layers is mounted on a motherboard and exposed to a thermal cycle—even when the cracks pass through the bottommost resin layer and reach the directly higher resin layer.
According to a first aspect of the present invention, there is provided a multilayer interconnect board comprised of a plurality of stacked cloth-reinforced resin layers with at least one layer of interconnect patterns formed at a stacking interface of the resin layers, wherein an interconnect pattern is formed at a stacking interface between a bottommost resin layer provided at its bottom surface with lands for bonding with external connection terminals and a directly higher resin layer while avoiding portions corresponding to the lands.
According to a second aspect of the present invention, there is provided a multilayer interconnect board comprised of a plurality of stacked cloth-reinforced resin layers with at least one layer of interconnect patterns formed at a stacking interface of the resin layers, wherein a full surface interconnect pattern is formed over substantially the entire surface of a stacking interface between a bottommost resin layer provided at its bottom surface with lands for bonding with external connection terminals and a directly higher resin layer.
According to a third aspect of the present invention, there is provided a multilayer interconnect board comprised of a plurality of stacked cloth-reinforced resin layers with at least one layer of interconnect patterns formed at a stacking interface of the resin layers, wherein no interconnect pattern is formed at a stacking interface between a bottommost resin layer provided at its bottom surface with lands for bonding with other external connection terminals and a directly higher resin layer.
According to a fourth aspect of the present invention, there is provided a multilayer semiconductor device comprised of such a multilayer interconnect board and a semiconductor chip carried on the same.
REFERENCES:
patent: 4778950 (1988-10-01), Lee et al.
patent: 5831333 (1998-11-01), Malladi et al.
patent: 6323436 (2001-11-01), Hedrick et al.
Meier Stephen D.
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
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