Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-24
2003-09-23
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S069000
Reexamination Certificate
active
06624477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for manufacturing an insulated gate type semiconductor device on an insulating substrate (which means, throughout the specification, any substance with an insulating surface, and includes not only insulating materials such as glass, but all semiconductors, metals and other materials with an insulating layer thereon, unless otherwise indicated), and forming an integrated circuit which comprises a plurality of such devices. The semiconductor device according to the present invention may be used as a thin film transistor (TFT) for active matrixes of liquid crystal display devices, etc., driving circuits of image sensors, etc., SOI integrated circuits and conventional semiconductor integrated circuits (microprocessors, microcontrollers, microcomputers, semiconductor memories, etc.).
2. Description of the Related Art
Up to now, it is widely known that TFTs (thin film transistors) are utilized as devices integrated on glass substrates for active matrix type liquid crystal display devices, image sensors, etc. FIGS.
3
(A) to
3
(E) show schematic diagram of the cross section of a TFT of the prior art, and it shows an exemplary flow chart of a preparation process therefor. The one shown in FIGS.
3
(A) to
3
(E) is an insulated gate field effect transistor with a thin film of silicon semiconductor positioned on a glass substrate (hereunder, abbreviated to TFT). The preparation process will be explained in brief below. In FIG.
3
(A), a reference numeral
301
indicates a glass substrate, and on this glass substrate
301
there is formed an underlying silicon oxide film
302
(around 2,000 Å thick) on which in turn an active layer
303
in the form of an island composed of a silicon semiconductor film is formed. This silicon semiconductor film has a thickness of approximately 500-2,000 Å, and is noncrystalline (amorphous) or crystalline (a polycrystalline, microcrystalline or the like). Formed on the active layer is a 1,000-1,500 Å thick silicon dioxide film
304
which forms a gate insulating film.
Next, a gate electrode
305
is formed with doped polycrystalline silicon, tantalum, titanium, aluminum, etc. [FIG.
3
(B)]. Further, with this gate electrode as the mask, an impurity element (phosphor or boron) is introduced by means such as ion doping, thereby forming source/drain regions (impurity regions)
306
in the active layer
303
in a self-aligning manner. The section of the active layer under the gate electrode with no impurity introduced therein is a channel-forming region
307
[FIG.
3
(C)].
In addition, the doped impurity is activated with a laser, flash lamp or the like [FIG.
3
(D)].
Then, a silicon oxide film is formed by means such as plasma CVD, APCVD or the like to provide an inter-layer insulator
307
. Furthermore, through this layer insulator, there is formed a contact hole on the source/drain regions, and a metallic material such as aluminum is used to form a wiring/electrode
308
which connects with the source/drain [FIG.
3
(E)].
For such TFTs of the prior art, it is necessary to reduce the sheet resistance for the improvement of the performance particularly, field mobility and subthreshold characteristics (S value). For the above purpose, the following three techniques have been presented.
1) The doping amount (concentration) of impurities is increased;
2) The activation energy (the intensity of the laser or the flash lamp) is increased considerably; and
3) The distance between the channel-forming region
307
and the metal electrode (z in the drawing) is shortened.
Relating to item 1), however, the increase in the doping amount causes a prolonged treatment time and results in a lower throughput, and also presents an additional problem in that the damage to the active layer and the gate insulating film
304
becomes severer. Particularly, though a method wherein a gas containing a doping element is made plasmic and accelerated for injection (ion doping or plasma doping method) is certainly excellent from the viewpoint of mass production, at the same time it has a drawback in that the accelerated ions contain many atoms of hydrogen and other elements which tends to heat the substrate in excess. This drawback becomes more notable at a higher plasma density.
Additional problems are that the elements are damaged by heating caused by doping, or the photo resist used as the mask for doping undergoes carbonization, thus becoming extremely difficult to be removed.
Also relating to item 2), the active layer and the gate electrode peel off at high energy, resulting in a lower yield of TFTs. The throughput is reduced either. For example, if a laser is employed, the energy of the laser cannot be changed considerably, and thus it becomes necessary to increase the focusing degree of the beams for a larger energy density. This inevitably leads to a reduced area of the beams which in turn results in a prolonged treatment time for the same area.
Further, item 3) above depends on the accuracy of the mask alignment, so much improvement of the characteristics cannot be expected. Particularly, in the case where a glass substrate is used as the substrate, shrinkage of the glass substrate during the heating steps (various annealing steps are required) is a serious obstacle to proper mask alignment. For example, a glass substrate over 10 cm square subjected to thermal treatment at around 500° C. readily undergoes shrinkage of around several microns. Accordingly, in practice the distance z is set to 20 &mgr;m or so to leave a margin. In addition, if the value of z is small, then the parasitic capacity between the gate electrode
305
and the source/drain electrodes
308
is increased correspondingly, and this increase adversely affects the performance of the TFT.
Another drawback resides in that, for the formation of a contact hole in the source/drain regions
306
, it is required to conduct a somewhat excessive etching procedure in order to ensure proper formation of the contact hole, and thus the distance denoted by z cannot be shortened indefinitely. For the foregoing reasons, it is extremely difficult to make a further reduction of the parasitic capacity of the source/drain regions of a TFT of the prior art.
SUMMARY OF THE INVENTION
The present invention is intended to solve the above problems, thereby providing a TFT with advanced characteristics, by substantially shortening the distance between the channel-forming region and the source/drain region and further reducing the resistance between them. It is another object of the invention to accomplish the above while facilitating mass production.
In accordance with the primary aspect of the invention, source and drain regions of a TFT are provided with a metal silicide layer having a relatively low resistivity. Thereby, the effective distance between a gate and a source/drain electrode can be reduced.
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paten
Konuma Toshimitsu
Takemura Yasuhiko
Zhang Hongyong
Jackson Jerome
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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