Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2001-10-16
2003-09-23
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S189110, C365S196000, C365S195000
Reexamination Certificate
active
06625065
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for masking DQ bits (data bits) that are input into a semiconductor memory by a memory controller.
In contemporary memory bus systems, during so-called burst writing, bits that are transmitted but are not to be read into the memory, such as a DRAM for example, are prevented from being read in by activation of an additional DQM terminal or pin. Data bits constitute an example of such bits that are not to be read into the DRAM.
In a memory controller, a DQ signal and a DQM signal are generated by a DQ logic unit and by a DQM logic unit, respectively. The DQ signal containing bits n−2, n−1, . . . , n+3, n+4 passes from the DQ logic unit via a driver to a DRAM receiver. The DQM signal is also fed to the DRAM receiver via a driver.
The DQM signal has a high level and a low level. If the DQM signal assumes its low level between two instants of time, then the bits n+1, n+2, n+3 of the DQ signal are masked at the same time as the low level in the DRAM receiver. The masked bits n+1, n+2, n+3 do not pass to a dynamic random access memory (DRAM) connected downstream of the DRAM receiver.
In this known method, then, the DQ signal and the DQM signal are transmitted by the memory controller externally to the DRAM or the DRAM receiver. As a result, the temporal coordination of the DQ and DQM signal is extremely critical and susceptible to changes in the line routing on a printed circuit board (“PCB routing”) and also jitter phenomena (voltage fluctuations, CLK or clock instabilities).
Moreover, it should be noted that the line routing for the DQM signal requires additional space and this line routing must be coordinated extremely accurately with the line routing for the DQ signal. In other words, the respective line lengths to be routed for the two signals and must be complied with exactly. All this leads to major problems in modules containing a plurality of DRAMs with a high packing density.
Finally, it should also be considered that additional pins are required in the DRAM receiver for the DQM signal, corresponding connectors in the module being made complicated as a result of this.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for masking DQ bits which overcomes the above-mentioned disadvantages of the prior art methods of this general type, which can be employed especially for increasing packing densities of memory modules and at high clock frequencies and largely eliminates routing problems.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for masking DQ bits that are input into a semiconductor memory by a memory controller. The method includes changing a voltage level of the DQ bits to be masked, during a time window, from a normal voltage level to a deactivating voltage level which deviates from the normal level. The DQ bits having the deactivating voltage level, are masked DQ bits and are not read into the semiconductor memory.
In the case of the method of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that the DQ bits to be masked are fed to the semiconductor memory with a changed, in particular increased, voltage level relative to unmasked DQ bits.
The method according to the invention thus introduces for the DQ bits a changed, preferably increased, masking voltage level. If the DQ bits or the DQ signal are or is at the changed or increased voltage level, then the corresponding bits are masked. Therefore, at a DRAM receiver only one terminal is required for the DQ signal or for setting the masking thereof. Thus, a considerable amount of space is saved, which results in a great advantage for the construction of the module.
Problems on account of erroneous co-ordination or a lack of coordination between the DQ signal and the DQM signal are largely avoided since the setting to the normal or increased voltage level for the DQ signal is already performed in a driver logic unit in the memory controller. The short signal paths also largely preclude time-critical problems on account of routing on a printed circuit board and also jitter phenomena and clock instabilities.
In accordance with an added mode of the invention, there is the step of using a dynamic random access memory as the semiconductor memory and the DQ bits are input into the dynamic random access memory.
In accordance with another mode of the invention, there is the step of generating the DQ bits with the deactivating voltage level relative to unmasked DQ bits in a driver circuit with a driver logic unit.
In accordance with a further mode of the invention, there is the step of providing the driver circuit and the driver logic unit in the memory controller.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for masking DQ bits, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4291221 (1981-09-01), Muehlbauer et al.
patent: 27 53 607 (1978-06-01), None
patent: 28 28 822 (1980-01-01), None
Gall Martin
Schaefer Andre
Elms Richard
Greenberg Lawrence A.
Hur Jung H.
Mayback Gregory L.
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