Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-15
2003-04-29
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06557153
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field electronic design automation (EDA). More specifically, embodiments of the present invention relate to an EDA system having an improved physical design system for hierarchical integrated circuit designs.
BACKGROUND ART
An electronic design automation (EDA) system is a computer system used for designing integrated circuit (IC) devices. The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist or automate most steps of this design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or “cells.” Such a design is too large for a circuit designer or even an engineering team of designers to manage effectively without computer systems.
In general, the EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation, for instance. A netlist is a description of the electronic circuit which specifies what cells compose the circuit and which pins of which cells are to be connected together using wires (“nets”). Importantly, the netlist does not specify where on a circuit board or silicon chip the cells are placed or where the wires run which connect them together. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. A single node can have multiple fan-ins and multiple fan-outs. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques.
FIG. 1
illustrates a typical integrated circuit design netlist that includes a number of hierarchical organized cells including a top level block
40
having a number of lower level circuit blocks
10
-
30
within. Each circuit block
10
-
30
includes a number of cells and or other blocks.
Once the netlist is complete, the actual physical size, dimensions, geometry and placement of the cells within the blocks can be determined. Determining this geometric information is the function of an automatic placement process and an automatic routing process, both of which are parts of the “physical design” process and are typically computer programs. The designer supplies the netlist into the computer implemented automatic cell placement process. The automatic placement computer program finds a location for each cell on a circuit board or silicon chip. The locations are specified, typically, in two dimensional spatial coordinates, e.g., (x, y) coordinates, on the circuit board or silicon chip. The locations are typically selected to optimize certain objectives such as wire length, wire routibility, circuit speed, circuit power consumption, and/or other criteria, and typically subject to the condition that the cells are spread evenly over the circuit board or silicon chip and that the cells do not overlap with each other. The output of the automatic cell placement process includes a data structure including the (x, y) position for each cell of the design.
Typically, placement is done in two steps including a first coarse placement process, then detailed a placement process. The coarse placement process finds approximate cell locations which optimize the desired metrics and spreads cells evenly across the silicon chip or circuit board. In the output data structure, some cells still overlap and no cells are in legal site locations, so the coarse placement needs to be legalized before the circuit can be fabricated. The detailed placement inputs the data structure output by the coarse placement and generates the detailed placement which does not have overlap and all are located on legal sites.
Next, the designer supplies the netlist and the cell location data structure, generated by the placement program, to a computer implemented automatic wire routing process. This computer program generates wire geometry within data structure. The wire geometry data structure and cell placement data structure together are used to make the final geometric database needed for fabrication of the circuit.
In executing the above physical design programs or “design tools,” many low level commands with associated parameters, options, variables and target databases are required. In some instances, up to 1,000 of these commands may be required to merely place one block. The commands perform low level functions for the design tools, e.g., a placer, such as: 1) initializing the placer for placement; 2) performing placement on a block; 3) evaluating the result; 4) formatting the data so that it can be understood; and 5) preparing the data for the next stage in the physical design process. Therefore, while the concept of performing a placement on a block can be abstracted to a high level operation, the actual commands given to the design tool to implement that operation are quite volumous.
Furthermore, physical design tools need to be executed on each block separately and then on the whole design. Separate sets of commands are required for each block that is to be processed. During the placement, other design tools may be required to check for any design rule violations or to perform optimizations, or to add special resources such as clocks and power lines, etc. The above process is then repeated for routing. As a result, multiple sets of commands are required for each physical design process to be completed and these commands are repeated over each block. In short, the actual command set required of the designer to merely place and route the netlist
40
of
FIG. 1
may require tens of thousands of low level commands which need to be input to the physical design tools in a particular order.
In an effort to address the daunting task of managing these commands, chip designers have written small “execute” programs that function to access a block of the netlist and depending on which block is obtained, apply a predetermined set of commands to the block involving the physical design tools. Once a block is processed, the next one is automatically obtained. Loops can be placed in the programs for processing multiple blocks in the same way, e.g., using the same set of commands. However, the computer time required to perform a place and route on a typical design is very long. Should there be a problem with the execute program, or a problem with the placement or routing of the netlist, or a problem in one of the commands, then the entire execute program needs to be re-run from scratch once the problem is isolated and fixed. Therefore, this prior art approach is not very efficient in the face of design errors or program bugs which are always present. Furthermore, although this prior art approach helps to automate some of the designer's job, it still requires that in the development or modification of the execute program, the designer needs to use and edit the low level, volumous detailed commands. As such, this development process can be tedious, error-prone and time consuming.
Another prior approach to solving the problem of dealing with these low level commands is utilize a program such as the UNIX Make, which is well known and commercially available. The program, Make, allows dependency graphs to be used indicating the input and the output of certain nodes, with each node representing a design tool task to be performed. In order to place and route the netlist, the graphs are analyzed to determined which nodes need which data and the appropriate node executio
Dahl Peter
Dickinson Byron
Levine Margie
Rodman Paul
Levin Naum
Reshape, Inc.
Siek Vuthe
Wagner , Murabito & Hao LLP
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