Variable capacitor and memory device employing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Voltage variable capacitance device

Reexamination Certificate

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C257S600000, C257S312000

Reexamination Certificate

active

06583495

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Korean Application No. 00-59649, filed Oct. 11, 2000, in the Korean Patent Office, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a variable capacitor and a memory device employing the same, and more particularly to a variable capacitor capable of varying its capacitance, and a memory device capable of recording multiple values in unit memory cells by using the variable capacitor.
2. Description of the Related Art
Capacitors are circuit devices for storing electric energy, which are almost essentially employed in diverse electric circuits. In general, plural capacitors of varied types are used in an electric circuit.
Such capacitors are mainly classified as fixed capacitors and variable capacitors. Variable capacitors having large capacitances are generally used for mechanically varying the capacitances, which are mainly employed for filter circuits and power supplies.
Only fixed capacitors have been employed in conventional integrated circuits.
In general, integrated circuits manufactured through a semiconductor manufacturing process have respective electric devices reduced into minimized and optimized lithography scales in sizes in order to increase the integration efficiency. In such micro scales, forming highly precise micro patterns without errors on a semiconductor based on the existing lithography and etching processing technologies is extremely difficult. Accordingly, errors occur frequently in the manufacturing process with respect to the capacitances of fixed capacitors. Further, there exists a problem in that follow-up modifications or tuning can not be done with respect to the integrated circuit for apparatuses requiring precise capacitances if errors occur in the capacitances of capacitors manufactured through the semiconductor manufacturing process.
That is, since the integrated devices having lots of integrated electronic devices include capacitors formed therein of which capacitances can not be varied according to necessity, there exists another problem in that the defects of the integrated devices on the manufacture can not be cured as well as the problem that the integrated devices can not be compatibly used for a specification of an electronic unit.
In the meantime, in case of RAMs and flash memories as examples of the integrated circuits, they are constructed to store data in a binary value by means of one transistor and one capacitor.
Studies are steadily being conducted for increasing the data storage densities of such memory devices.
FIG. 1
is a cross-sectioned view for showing a conventional memory device.
Referring to
FIG. 1
, a memory device
10
has a transistor
12
formed on a substrate
11
and a capacitor
17
. Reference numerals
18
a,
18
b
and
18
c
indicate insulation layers.
The transistor
12
includes a source (S)
13
, a drain (D)
14
, and a gate (G)
15
which are spaced apart from each other.
The capacitor
17
is constituted with a first electrode
17
a
formed to be electrically connected to the source
13
through a conductive connection layer
16
, a ferroelectric substance
17
b,
and a second electrode
17
c.
The memory device
10
, as shown in the equivalent circuit of
FIG. 2
, receives write/read signals through the gate
15
connected to a control line
21
, and charges the capacitor
17
to a predetermined voltage Vs and discharges a charged voltage through the drain
14
connected to a data line
22
, to thereby write and read binary data.
The size of the memory cell should be reduced in order to increase the data storage density in such a conventional memory device. By the way, the size of the cell determining the data storage density is defined by variables such as a possible minimum pattern size (F) by the lithography, a clearance area (f) necessary for arrangements between cells, a minimum switching electric charge quantity Qswo, and the like.
In case of a DRAM as an example, the following relationship is obtained among a capacitance Co of the capacitor
17
, a cell driving voltage Vdd, a switching electric charge quantity Qswo, and an area Ao(&mgr;m
2
) of the capacitor
17
.
Co×
10
−15
×Vdd=Qswo×Aox
10
14
  {Formula 1}
The following Formula 2 is obtained from rewriting Formula 1.
Qswo=Co×Vdd/
10×
Ao
  {Formula 2}
Where, in case that Co=30fF and Vdd=3V are applied with respect to the respective variables, Qswo=9/Ao is obtained. Further, in case that a dielectric substance used for the capacitor
17
is a ferroelectric substance having the QSW of about 20 &mgr;C/cm
2
, the area Ao of the capacitor
17
requires an area of about 0.23 &mgr;m
2
. That is, it is difficult to form one side of the capacitor
17
less than 0.47 &mgr;m.
Accordingly, the memory device
10
using the conventional fixed capacitor
17
has some restrictions in increasing the data storage density since difficulties exist in reducing the area of a unit cell storing data in a binary scale to an area less than a certain size.
SUMMARY OF THE INVENTION
The present invention is devised to solve the problems stated above, and it is an object of the present invention to provide a variable capacitor which can be manufactured by using semiconductor micro machining technologies and of which capacitance can be varied according to necessity.
It is another object of the present invention to provide a memory device in which data per cell can be stored in multiple values by applying the variable capacitor.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the invention.
In order to achieve the above and other objects, the variable capacitor comprises a first electrode formed above a substrate; a second electrode installed to be able to float with respect to the first electrode and movable back and forth with respect to the first electrode; and a device to vary a capacitance, one end of which is connected to the second electrode and mounted with respect to the substrate to move the second electrode with respect to the first electrode in accordance with a voltage signal input through a driving electrode exposed externally.
Preferably, the device to vary the capacitance comprises a piezoelectric device contracted and expanded in response to a voltage input through the driving electrode.
Further, the variable capacitor comprises first and second electrodes formed at a distance spaced apart from each other above a substrate; a dielectric substance installed to move back and forth in a space between the first and second electrodes; and a device connected to the dielectric substance and formed above the substrate to move the dielectric substance back and forth in accordance with a voltage input through a driving electrode exposed externally, to vary a capacitance.
In order to achieve the above and other objects as stated above, the memory device according to the present invention comprises a transistor having a source, a gate, and a drain formed above a substrate, which are spaced apart from each other; and a variable capacitor connected to the source and having a device varying a capacitance of the capacitor. Note that any type of transistor may be used in the alternative including or having an emitter, collector, and a drain.
Preferably, the capacitor includes a first electrode formed above the substrate to be electrically connected to the source; and a second electrode formed to have a distance with respect to the first electrode which can be varied by the device to vary the capacitance.
The device to vary the capacitance includes a driving electrode extended externally; and an actuator mounted with respect to the dielectric substance, spaced apart by a predetermined distance along a direction opposite to the first electrode, and movi

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