Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-25
2003-04-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06553553
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for designing the layout of a semiconductor device, and particularly, to a method for designing the layout of a standard cell semiconductor device.
FIG. 1
is a schematic diagram showing the layout of a prior art standard cell semiconductor device
1
. The semiconductor device
1
includes a plurality of cell rows
2
. To lay out logic cells A, which are provided with logic functions, the logic cells A are first arranged in each cell row
2
. Then, spacer cells B are arranged in vacant areas that are not occupied by-the logic cells A (vacant areas) to connect the logic cells A to a power source (not shown). The spacer cells B each includes dimension data and power line data. The spacer cells B are arranged to correspond with the dimensions of the vacant areas to connect the power lines of the logic cells A.
In recent years the scale of semiconductor device
1
has been increasing. This has resulted in the arrangement having auxiliary functions on the semiconductor device
1
. Auxiliary cells may include, for example, a master slice basic cell for making logic changes or for adjusting timing with metal modification, an antenna effect diode cell for preventing characteristic deterioration during the fabrication process, and capacitance cells for preventing power supply noise.
The size of each vacant area is determined by the layout of the logic cells A. Each type of auxiliary cells has a different size. Thus, it is difficult to arrange auxiliary cells of different dimensions, and the designing of the semiconductor device
1
may be time consuming.
SUMMARY OF THE INVENTION
This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the present invention is devised for laying out a plurality of auxiliary cells between logic cells in a semiconductor device, wherein the auxiliary cells include representative auxiliary cells and each of the auxiliary cells has a predetermined dimension.
The method of the present invention entails the following steps: 1) temporarily arranging the representative auxiliary cells in a plurality of vacant areas that are not occupied by the logic cells; 2) obtaining the number and the total area of the temporarily arranged representative auxiliary cells having the same dimension; and 3) arranging a plurality of the functional auxiliary cells in place of the temporarily arranged representative auxiliary cells, based on the number and total area of the representative auxiliary-cells having the same dimension and the specification of the semiconductor device, wherein each of the functional auxiliary cell has a dimension and a function that are in accordance with the dimension and a selected function of its corresponding temporarily arranged representative auxiliary cell.
In the method of the present invention, the temporary arrangement of the representative auxiliary cells can be carried out by arranging the representative auxiliary cells largest to smallest in dimension. Moreover, the auxiliary cells can be registered in a cell library and include dummy cells used for the temporary arrangement, wherein each of the dummy cells has only dimension-related data. Further, the functional auxiliary cells can be arranged, for instance, after deleting the temporarily arranged representative auxiliary cells; or exchanged with the temporarily arranged representative auxiliary cells, wherein the exchanged auxiliary cells have the same dimensions. And the arranging step includes selecting a functional auxiliary cell for each of the temporary arranged representative auxiliary cells.
The present invention provides an apparatus includes a processor configured to carry out the above method. In the apparatus of the present invention, the auxiliary cells may be registered in a cell library and include dummy cells used for the temporary arrangement, wherein each of the dummy cells has only dimension-related data.
The present invention further provides a computer readable storage medium, containing a program code instructed to perform the method described above.
REFERENCES:
patent: 5012427 (1991-04-01), Kuribayashi
patent: 6054872 (2000-04-01), Fudanuki et al.
patent: 6308307 (2001-10-01), Cano et al.
patent: 01140640 (1989-06-01), None
patent: 08138383 (1996-05-01), None
patent: 10074840 (1998-03-01), None
patent: 10092940 (1998-04-01), None
patent: 2001284456 (2001-10-01), None
Fujitsu Limited
James Lin Sun
Smith Matthew
Staas & Halsey , LLP
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