Semiconductor memory

Details Semiconductor memory Semiconductor memory

2002-07-05

2003-07-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S051000, C365S063000

Reexamination Certificate

active

06597599

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system LSI on which a DRAM is merged, and more particularly, to a semiconductor memory such as a DRAM used for a system LSI fabricated in a logic process.
2. Description of Related Art
In order to mount a DRAM on a system LSI by means of a DRAM and logic hybrid process, a process step for forming a capacitor of a DRAM core having a complicated three-dimensional structure and further a planarization process step for reducing a difference in level (steps on the substrate) caused by the capacitor of the DRAM core having the three-dimensional structure are required in addition to a usual CMOS logic process. As a result, the number of the process steps greatly increases, and thereby the cost of the chip increases.
On the other hand, among merged memories that can be formed in a complete CMOS logic process is a SRAM. Conventionally, the SRAM has been used for a cache memory, a register file memory, and the like for a processor. However, in a personal digital assistant, in order to make its system configuration simple, the SRAM is widely used as the main memory. This is because the SRAM does not require a complicated memory control relating to a refresh operation that is indispensable to DRAMs, and further the SRAM is manageable.
However, also in the personal digital assistant, recently, its function has been greatly improved to process moving images, and required a large-capacity memory.
In the DRAM, with the progress of a microfabrication process, the size of the memory cell has shrunk, and the cell size of 0.3 &mgr;m
2
has been achieved in 0.18 &mgr;m DRAM process for instance. On the other hand, in the SRAM, its memory cell consists of six transistors of p-ch and n-ch in total, and the SRAM is under the restrictions of an isolation distance between the p-well and n-well though the microfabrication process has become advanced. Accordingly, the SRAM has not shrunk in the size of the memory cell as much as the DRAM has done. The size of a SRAM memory in 0.18 &mgr;m CMOS logic process is about 7 &mgr;m
2
, which is 20 times larger than that of a DRAM memory cell. Consequently, in the SRAM, since the chip size is extremely larger as the capacity is larger, merging a 4 M bits or more SRAM is extremely difficult.
In view of such a situation, if a merged memory having a large capacity is constituted by use of a DRAM memory cell fabricated by a process similar to the CMOS logic process, a merged memory that is not as small as the memory size of a usual DRAM but sufficiently smaller than the memory size of the SRAM can be fabricated while holding down the rising of chip cost.
FIG. 10
is a layout view showing the layout of conventional DRAM memory cells. Referring to
FIG. 10
, field pattern FL is formed in a rectangular shape, and a plurality of them are arranged in a close packed layout in a matrix. Reference character W
1
denotes the width of the active region of a MOS Tr (transistor), and W
2
denotes the width of the active region of a capacitor.
Cell plate electrodes CP
0
-CP
3
are arranged on the active regions of the capacitors of field patterns FL through capacitor insulation films, and subword lines WL
0
-WL
3
are arranged by two on field patterns FL through gate oxide films, and serves as the gate electrodes of MOS Trs.
Bit lines ZBL
0
, BL
0
, ZBL
1
, and BL
1
each are arranged on cell plate electrodes CP
0
-CP
3
and subword lines WL
0
-WL
3
through insulation films, and orthogonal to subword lines WL
0
-WL
3
. Bit line contacts BC each connect bit lines ZBL
0
, BL
0
, ZBL
1
, and BL
1
to the impurity-diffused areas of the MOS Trs. Reference characters MC
1
and MC
2
each denote the memory cells, and sense amplifiers S/A differentially amplify and output the potential of each of a pair of bit lines ZBL
0
and BL
0
, and a pair of bit lines ZBL
1
and BL
1
.
The operation of the conventional memory cells will next be described.
A row active command is given, and under row selecting operation, one of subword lines WL
0
-WL
3
is selected in
FIG. 10
for instance. Thus, two memory cells each are connected with a pair of the bit lines.
For instance, when subword line WL
0
is selected, memory cells MC
1
and MC
2
are connected with the pair of bit lines ZBL
0
and BL
0
. H level data is memorized in one of memory cells MC
1
and MC
2
, and L level data is memorized in the other, thereby memorizing or storing one bit information by taking a pair of memory cells MC
1
and MC
2
as a memory unit in two cell mode (twin cell mode).
Sense amplifier S/A connected with the pair of bit lines ZBL
0
and BL
0
differentially amplifies and outputs the potential of the pair of bit lines ZBL
0
and BL
0
.
Since the conventional semiconductor memory or storage device has been arranged as mentioned above, a voltage (data) memorized is read out by sense amplifier S/A from the impurity diffused area of the MOS Tr connected therewith through the pair of bit lines ZBL
0
and BL
0
, and bit line contact BC. However, as shown in
FIG. 10
, because the active region of the MOS Tr and the active region of the capacitor of field pattern FL are formed such that they have the same width (W
1
and W
2
), the gate capacitance of the MOS Tr and the junction capacitance of the impurity diffused area are inevitably large. As a result, there is a drawback that the rise of the readout voltage is slow due to the influence thereof, and thereby the high-speed access cannot be performed.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-mentioned drawback. An object of the present invention is to provide a semiconductor memory having a layout of memory cells capable of rising promptly a readout voltage to allow high-speed access.
According to a first aspect of the present invention, there is provided a semiconductor memory including: in a plurality of field patterns arranged in a close packed layout in a matrix, a cell plate electrode which is arranged on the active region of the capacitor of the field pattern, a word line which is arranged by two on the field pattern, a bit line which is arranged on said cell plate electrode and to be orthogonal to said word line, and which are connected to an impurity diffused area of the transistor of said field pattern, and a sense amplifier for differentially amplifying and outputting each potential of a pair of bit lines composed of the two bit lines, wherein the width of the active region of the transistor of the field pattern is formed narrower than that of the active region of the capacitor.
In such a way, in the field pattern, the gate capacitance of the transistor connected with the bit line, and the junction capacitance of the impurity diffusion area can be reduced as compared with the gate capacitance and junction capacitance in the rectangular field pattern, thereby obtaining a layout of memory cells in which a readout voltage rises quickly to thereby perform high-speed access.
In addition, in the field pattern, the occupancy rate of the active region of the transistor in the cell size of one bit can be reduced, and thereby an optimum layout for the CMP (chemical, mechanical, and polishing) processes can be obtained upon the formation of trench isolations.


REFERENCES:
patent: 5523965 (1996-06-01), Kaga et al.
patent: 5574680 (1996-11-01), Kim et al.
patent: 6137713 (2000-10-01), Kuroda et al.
patent: 6314017 (2001-11-01), Emori et al.
patent: 61-274357 (1986-12-01), None

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