Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-05-01
2003-09-30
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S111000
Reexamination Certificate
active
06629224
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for operating a semiconductor memory device having a plurality of operating modes and a semiconductor memory device having a plurality of operating modes.
2. Description of the Related Art
Conventionally, semiconductor memory devices such as DRAMs receive a different address signal from the same address terminal at twice in order to reduce the number of terminals. Such a semiconductor memory device receiving multiplexed address signals can be molded in a small package in spite of its large memory capacity.
A synchronous DRAM (SDRAM) is known as another semiconductor memory device to receive multiplexed address signals. The SDRAM is a memory device that operates input/output interfacing circuits at high speed in synchronization with a clock signal and write and read data at high speed.
The SDRAM is capable of performing read and write operations in a plurality of memory cells connected with a same word line, at high speed. However, in memory cells connected with different word lines, the word lines must be selected at a timing similar to that in the prior art DRAMs. Therefore, an access time in a random access is equivalent to that in the DRAMs.
An operating mode of SDRAMs is determined upon inputting a command once; then, the SDRAMs perform the operating mode determined. Due to this, a number of terminals for receiving multiple command signals such as a chip select signal (/CS), row address strobe signal (/RAS), column address strobe signal (/CAS), write enable signal (/WE), and clock enable signal (CKE) are required. In addition, as the sequence of inputting commands is not predetermined, a timing of performing a precharge operation of a bit line can not be generated inside of a chip. Accordingly, precharging a bit line needs to be performed by supplying a command from the exterior of the chip.
In recent years, fast cycle RAM (FCRAM) have been developed as DRAMs whose operation cycle is significantly shortened to perform data read/write operation at high speed during random accessing.
The FCRAM is designed so that its internal operation is divided into three stages. An operation in each stage is completed automatically. This makes it possible to perform a pipeline processing not only for data input/output units but also for an address accepting an operation and an operation of a memory core unit. The use of such pipeline processing makes it possible to shorten the operating cycle. Additionally, as the FCRAM is designed to achieve shortening an access time as a top priority, address terminals are non-multiplexed and all address signals are supplied at the same time of inputting a command. Upon inputting a single command, an operating mode is determined and then the predetermined operating mode is performed.
The above-described SDRAMs have a disadvantage that these require a great number of command input terminals. An increase in number of command input terminals complicates a configuration of circuit, which controls a command input, on printed wiring boards.
The above-noted FCRAMs have a disadvantage that, when compared to DRAMs and SDRAMs having equal memory capacities, they require more terminals because of non-multiplexed addressing. An increase in terminal number results in increases in associative components such as address pads and address input circuits and others, which causes a problem that the chip size gets larger. Another disadvantage is that such increase in terminal number can cause the package size to likewise increase. In particular, in the case CSP (chip size package) which has been becoming a mainstream in the art, balls connected to a printed wiring board are laid out in the form of two-dimensional arrangement thereon. This may result in an increase in size of package depending upon the number of terminals.
SUMMARY OF THE INVENTION
An object of the present invention is to reduce the number of terminals necessary for inputting commands and addresses.
Another object of the present invention is to prevent an increase in chip size and its package size by reducing the number of terminals.
Still another object of the present invention is to retain an operation cycle at high speed even when terminals decrease in number.
Further object of the invention is to especially accept a signal at high speed in order to retain an operation cycle at high speed.
According to one of the aspects of the method for operating a semiconductor memory device in the present invention, signals supplied to predetermined terminals are accepted as commands at a plurality of times, the number of operating modes is sequentially narrowed down based on the command each time and an internal circuit is controlled according to the narrowed operating modes. Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. One example is that four or eight operating modes may be identified respectively when commands are accepted at two or three times at two terminals. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size.
According to another aspect of the method for operating, a semiconductor memory device in the present invention, commands are accepted at twice. The number of operating modes are narrowed down by the first command. At this time, a part of the circuit necessary for performing a predetermined operating mode among the narrowed operating modes is operated. Then, an operating mode is determined by the second command; when the operating mode is a predetermined operating mode, the remainder of the circuit is operated. Performing a part of the predetermined operating mode in advance makes it possible to shorten the access time even in the case of accepting commands at twice.
According to still another aspect of the method for controlling a semiconductor memory device in the present invention, a mode register setting mode without accompanying any internal operation is such that the operation can be completed within a predetermined period even when an operation is initiated after the receipt of the second command. Similarly, a data retaining mode does not require inputting /outputting data from/to the exterior so that the operation may be completed within a predetermined period even when the operation is initiated after the receipt of the second command.
According to yet another aspect of the method for controlling a semiconductor memory device in the present invention, it is unnecessary to accept information for setting the mode register together with the first command from an address terminal. Therefore, it is unnecessary to retain the information until the second command is supplied; as a result, it is possible to prevent the complication of a controlling circuit.
According to further aspect of the method for operating a semiconductor memory device in the present invention, the control necessary for shifting to the data retaining mode is performed when an operating mode determined by the second command is a data retaining mode. Thereafter, the control necessary for shifting to a standby mode is performed when a signal supplied to a predetermined terminal is set at a predetermined level during the data retaining mode. By monitoring a signal at a predetermined terminal other than by a command, it is possible to shift to another operating mode during a predetermined operating mode.
According to further aspect of the method for operating a semiconductor memory device in the present invention, the control necessary for shifting to a self refresh mode is performed when a signal supplied to a predetermined terminal is set at a predetermined level during an auto refresh mode. A difference between the auto refresh and self refresh modes is that the former is given a re
Sato Kotoku
Suzuki Takaaki
Uchida Toshiya
Yagishita Yoshimasa
Arent Fox Kintner Plotkin & Kahn
Elmore Reba I.
Fujitsu Limited
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