Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-25
2003-08-26
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06611945
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for propagating switching activity information in a digital network, and more particularly to a method for computing and propagating signal and switching probabilities through components in a combinatorial logic circuit.
2. Description of the Related Art
In electronic systems, power consumption is one of the factors determining efficiency and functionality of the system. With the proliferation of wireless and hand-held electronic devices such as palm top computers, cellular telephones, etc., power consumption has become an important factor to be considered in designing and manufacturing such electronic devices. Since power consumption of such electronic devices directly relates to battery size and duration of usage of the devices between charges, battery life has become one of the most important factors in such electronic devices.
To choose a battery for an electronic device, the expected power consumption of the electronic device has to be accurately computed. In order to design power-efficient electronic devices, it is necessary to estimate and optimize power consumed in each component (i.e., IC) of an electronic device. Accurate computation of power consumption can improve battery life by enabling the design process to alleviate power-related problems in an electronic device, such as electron migration, circuit timing degradation due to voltage drops, hot-electron degradation, etc.
For fabrication of logic circuits in electronic devices, complementary metal oxide silicon (CMOS) technology is most commonly used. For CMOS devices, a primary source of power consumption is “dynamic power”. Dynamic power is the power consumed when signals at inputs or output(s) of the CMOS circuit switch from one logic state to another logic state, for example, from logic “0” to logic “1” or from logic “1” to logic “0”.
A logic network performing a predetermined logic function may have a set of logic circuits each of which operates in accordance with a certain logic function. In such a logic network, a combinatorial logic function is performed by implementing a logic function of each logic circuit. Thus, to compute power consumed in such a logic network, it is necessary to compute power consumed in each of the logic circuits.
For computation of dynamic power (or switching power) in a logic circuit, it is necessary to compute the number of logic transitions per unit time of a signal at each node in the logic circuit. In terms of quantity, the number of logic transitions per unit time of a signal at Node i is called “switching probability (q
i
)”. In a synchronous digital network, switching probability (q
i
) represents a fraction of clock cycles during which a signal at Node i makes a transition.
Another quantitative term related to the switching probability (q
i
) is “signal probability (p
i
)” at Node i. Signal probability (p
i
) represents a fraction of time during which a signal at Node i has a value of logic “1”. The signal and switching probabilities (p
i
, q
i
) at Node i are among quantities that are collectively known as “signal statistics” of a signal at Node i.
Since dynamic power consumed in a logic circuit is substantially equal to summation of switching powers consumed in all the nodes of the logic circuit during transitions of signals at the nodes, power consumed in the logic circuit can be computed from the following equation:
Power
=
∑
i
C
i
V
2
q
i
(
1
)
where, “C
i
” is load capacitance, “V” is amount of voltage swing between logic “0” and logic “1”, and “q
i
” is switching probability at Node i. In Equation (1), a product of C
i
, V
2
, and q
i
is calculated with respect to Node i, and the summation is taken over all the nodes in the logic circuit.
To compute power consumed in a logic circuit using Equation (1), it is necessary to have values of switching probabilities at all nodes in the logic circuit. Assuming that signal statistics, including switching probabilities, at inputs of a logic circuit are known, power consumed in the logic circuit can be obtained using Equation (1) by computing switching probabilities at all nodes in the logic circuit. Such computation of switching probabilities at all the nodes can be accomplished by propagating the signal statistics at inputs of the logic circuit through various Boolean functions constituting a combinatorial function of the logic circuit. Thus, signal statistics of a logic circuit obtained from such a propagation depends on each Boolean function (1) and signal statistics at inputs of the logic circuit.
Conventional methods for propagating signal statistics, including signal and switching probabilities, into a logic circuit are disclosed, for example, in “Transition Density: A New Measure of Activity in Digital Circuits”, by F. Najm, February 1993, IEEE, Vol. 12, No. 2, pp. 310-323 (hereinafter “Najm”); and “Estimation of Activity for Static and Domino CMOS Circuits Considering Signal Correlations and Simultaneous Switching”, by T. Chou and K. Roy, October 1996, IEEE, Vol. 15, No. 10, pp. 1257-1264 (hereinafter “Chou et al.”).
Najm discloses formulas to compute signal and switching probabilities at the output of a node in the logic circuit using signal and switching probabilities at the inputs of the node. Najm assumes that input signals of a logic circuit are statistically independent and that only one of the input signals may make a transition at any given time.
Chou et al., mentioning that the formulae proposed by Najm have limitations in handling simultaneous switching of input signals of a node, proposes a method for more accurately propagating signal and switching probabilities into a logic circuit by extending the result in Najm. In “Probabilities Modeling of Dependencies During Switching Activity Analysis”, by Marculescu et al., February 1998, IEEE, Vol. 17, No. 2, pp. 73-83, the method (formulae) proposed by Chou et al. has been modeled in terms of Markov processes to provide a solution for propagation of signal and switching probabilities considering spatial-temporal correlations in analysis of the propagation.
However, the conventional methods for propagating signal and switching probabilities at inputs into a logic circuit are difficult to apply in practice for computing power consumed in the logic circuit. For example, in a simulation of propagating signal and switching probabilities through a network using the conventional methods, vectors are obtained at inputs of the network and then used for computing signal and switching probabilities at each of intermediate inputs and outputs of the network. Such a simulation is a time consuming and costly process. The Markov based process or the Boolean difference based process leads to highly complex computations in implementing the propagation of signal and switching probabilities.
Therefore, a need exists for a method for propagating signal and switching probabilities at inputs through a logic network by using a less complex and less time-consuming method of computing signal and switching probabilities with respect to each of logic circuits in the logic network. Further, it will be advantageous to provide a method for estimating and optimizing power consumed in a logic network using the propagation of signal and switching probability through the logic network.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for computing and propagating signal and switching probabilities through logic circuits in a combinatorial network to obtain signal and switching probabilities at output of the network.
It is another object of the present invention to provide a method for estimating power consumed in a logic circuit using the method of propagating signal and switching probabilities through the logic circuit.
It is still anther object of the present invention to provide a method for optimizing power consumed in a logic circuit using the method of power estimation and propagation of signal and switch
Farrahi Amir
Narasimhan Jagannathan
F. Chau&Associates, LLP
Siek Vuthe
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