Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-10-18
2003-06-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S301000, C438S529000, C438S652000, C438S656000
Reexamination Certificate
active
06579784
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a metal gate device which can be integrated with a salicide process on the source and drain regions.
2) Description of the Prior Art
Polysilicon gate electrodes are commonly used in CMOS devices. However, as device densities continue to increase beyond the 0.2 &mgr;m generation, polysilicon gates are adversely affected by poly depletion which can reduce performance by more than 15%. While metal gates are an attractive alternative, they are susceptible to metal migration during subsequent operations that are performed at elevated temperatures.
Another problem with existing metal gate processes is that the fluorine etch typically used to pattern the metal layer to define a gate electrode has poor selectivity for silicon dioxide. This poor selectivity causes poor gate oxide definition resulting in damage to the underlying silicon.
To avoid the fluorine etch of the metal layer, a replacement gate process can be used. In a replacement gate process, a dummy gate is formed of silicon dioxide or a polymer such as photoresist. An oxide layer is formed over the dummy gate. The oxide layer is planarized and the dummy gate is removed leaving a gate opening. Then, the desired gate material is deposited into the gate opening. One problem with existing replacement gate processes is that they are not easily integrated with a salicide process on the source and drain regions.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,731,239 (Wong et al.) shows a method of forming a poly/TiSi
x
gate with a separate salicide step to form TiSi
x
on the source and drain regions.
U.S. Pat. No. 4,908,332 (Wu) shows a process for forming a poly/metal gate. This process does not show or suggest the use the poly/SiO
2
/Si
3
N
4
substitutional gate or the poly/TiN/W gate electrode of the present invention. This process also does not show or suggest the integration of a salicide step on the source and drain regions.
U.S. Pat. No. 5,447,874 (Grivna et al.) shows a method for forming a two layer metal gate using a damascene/CMP process. This method does not provide the poly/TiN/W gate of the invention, and is not easily integrated with a salicide process on the source and drain.
U.S. Pat. No. 4,745,082 (Kwok) shows a substitutional gate method for forming a metal gate by metal deposition and CMP back.
U.S. Pat. No. 5,670,401 (Tseng) discloses a poly gate formed by a CMP process.
U.S. Pat. No. 5,395,799 (Yu) shows a poly/WSi
x
/SiN gate.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a metal gate integrated with a salicide process on the source and drain regions.
It is another object of the present invention to provide a method for forming a transistor gate and metal lines with low contact resistance, requiring reduced source and drain pick up area, and not affected by poly depletion.
It is yet another object of the present invention to provide a method for forming a metal gate with silicide overlying the source and drain regions and metal lines wherein subsequent processing does not require a high thermal budget.
To accomplish the above objectives, the present invention provides a method of forming a metal gate integrated with a salicide process on the source and drain regions.
The process begins by forming a gate dielectric layer and polysilicon/silicon dioxide/silicon nitride dummy gate layers over a substrate structure and patterning them to form a dummy structures. Lightly doped source and drain regions are formed by ion implantation. Spacers are formed on the sidewalls of the dummy gate. Source and drain regions are formed by implanting ions. A silicide layer is formed on the source and drain regions by depositing titanium/titanium nitride, performing a rapid thermal anneal, selectively removing unreacted titanium/titanium nitride using NH
4
OH
2
and performing a second rapid thermal anneal. A blanket dielectric layer is formed over the dummy structures. The blanket dielectric layer, the spacers and the silicon nitride layer of the dummy structures are planarized using a chemical mechanical polishing process. The silicon nitride layer and the silicon dioxide layer of the dummy structures are removed. A titanium nitride layer is formed over the polysilicon layer of the dummy structures, and a tungsten layer is deposited over the titanium nitride layer. The tungsten layer and titanium nitride layer are planarized using a chemical mechanical polishing process, thereby forming polysilicon/titanium nitride/tungsten structures. An inter-layer dielectric layer is formed over the polysilicon/titanium nitride/tungsten structures. A conductive plug is formed in the inter-level dielectric layer over the polysilicon/titanium nitride/tungsten structures. A metal-
1
pattern is formed over the conductive plug and the inter-level dielectric and patterned to form device interconnections.
The present invention provides considerable improvement over the prior art. Source and drain regions are formed prior to forming the metal gate, eliminating the need for high temperature processing after metal gate formation which could cause metal migration. The polysilicon/titanium nitride/tungsten gate electrode provides low contact resistance (~1 ohm/sq) while avoiding the poly depletion problem for small scale devices. Also, the integration of the salicide process on the source and drain regions provides low contact resistance at the source and drain, reducing the area required for long distance word line or bit line pick ups in memory circuits.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4745082 (1988-05-01), Kwok
patent: 4908332 (1990-03-01), Wu
patent: 5395799 (1995-03-01), Yu
patent: 5447874 (1995-09-01), Grivna et al.
patent: 5670401 (1997-09-01), Tseng
patent: 5731239 (1998-03-01), Wong et al.
patent: 5856225 (1999-01-01), Lee et al.
patent: 5966597 (1999-10-01), Wright
patent: 6033963 (2000-03-01), Huang et al.
patent: 6054355 (2000-04-01), Inumiya et al.
patent: 6093628 (2000-07-01), Lim et al.
patent: 6118161 (2000-09-01), Chapman et al.
patent: 6137137 (2000-10-01), Wu
patent: 6228722 (2001-05-01), Lu
Ackerman Stephen B.
Niebling John F.
Pompey Ron
Saile George O.
Taiwan Semiconductor Manufacturing Company
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