Microelectronic capacitor with barrier layer

Details Microelectronic capacitor with barrier layer Microelectronic capacitor with barrier layer

2001-09-06

2003-05-06

Nguyen, Cuong Quang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000

Reexamination Certificate

active

06559497

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to capacitor structures formed within microelectronic fabrications. More particularly, the present invention relates to passivated capacitor structures formed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Common in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprise a field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has formed thereover and electrically connected therewith a storage capacitor. Within a dynamic random access memory (DRAM) cell structure, a gate electrode of the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction into and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor layer which introduces or retrieves charge with respect to the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor integrated circuit microelectronic fabrication, and is thus essential in the art of semiconductor integrated circuit microelectronic fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic memory fabrication.
In that regard, as semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly difficult in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to reliably fabricate within dynamic random access memory (DRAM) cell structures storage capacitors with enhanced performance.
It is thus desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to provide methods and materials through which there may be reliably fabricated, with enhanced performance, capacitor structures.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming, with desirable properties, capacitor structures.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Tsu et al., in U.S. Pat. No. 5,573,979 (a method for forming a capacitor structure with a lower capacitor plate having a sloped surface, such as to avoid capacitor dielectric layer cracking when forming thereupon a capacitor dielectric layer); (2) Kirlin et al., in U.S. Pat. No. 5,976,928 (a chemical mechanical polish (CMP) planarizing method for forming, with enhanced fabrication efficiency, a ferroelectric capacitor structure within a microelectronic fabrication); and (3) Hartner et al., in U.S. Pat. No. 6,043,529 (a method for forming a capacitor structure with enhanced reliability by forming annularly surrounding a barrier layer interposed between a conductor stud layer and a lower capacitor plate layer within the capacitor structure an annular silicon nitride layer).
Desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for readily fabricating, with enhanced performance, capacitor structures.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the invention is to provide a capacitor structure for use within a microelectronic fabrication.
A second object of the present invention is to provide a capacitor structure in accord with the first object of the present invention, wherein the capacitor structure is reliably fabricated with enhanced performance.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a first capacitor plate. There is then formed upon the first capacitor plate a capacitor dielectric layer. There is then formed upon the capacitor dielectric layer a second capacitor plate. Finally, there is then formed upon the second capacitor plate a conductor barrier layer.
There is provided by the present invention a capacitor structure for use within a microelectronic fabrication, wherein the capacitor structure is readily fabricated with enhanced performance.
The present invention realizes the foregoing objects by forming upon an upper capacitor plate within a capacitor structure within a microelectronic fabrication a conductor barrier layer. The conductor barrier layer provides for attenuated interdiffusion and enhanced adhesion of the upper capacitor plate with respect to adjacent layers within the microelectronic fabrication within which is formed the capacitor structure.


REFERENCES:
patent: 5573979 (1996-11-01), Tsu et al.
patent: 5716875 (1998-02-01), Jones et al.
patent: 5976928 (1999-11-01), Kirlin et al.
patent: 6043529 (2000-03-01), Hartner et al.
patent: 6238934 (2001-05-01), Yang
patent: 6342712 (2002-01-01), Miki et al.

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