Semiconductor integrated logic circuit device using a pass...

Details Semiconductor integrated logic circuit device using a pass... Semiconductor integrated logic circuit device using a pass...

2001-02-15

2003-04-01

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C326S101000

Reissue Patent

active

RE038059

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and a method of producing the same. More particularly, the present invention relates to integrated circuit devices such as an application specific I.C. (ASIC), a microprocessor, a microcontroller, a digital signal processor, etc., and a method of efficiently producing them.
Systems such as gate arrays, standard cells, cell based ICs, etc., have been widely employed in the past to accomplish a large-scale logic circuit, in particular. A characteristic feature of these integrated circuits is that partial circuits referred to as “cells” are prepared in advance.
The term “cell” means a small scale logic circuit such as NAND, NOR, etc., for which layout of a mask pattern has already been finished. Generally, the positions of input/output terminals and an operation speed are determined besides the mask layout.
When information on this cell is gathered and registered to an auxiliary memory unit of a computer for computer aided design, it is referred to as a “cell library” (or sometimes “macrocell library”, “macro library”, “device library” and “standard cell library”).
If such a cell library for so-called “CAD (Computer Aided Design)” is prepaid in advance, an integrated circuit having an intended logic function can be accomplished by merely disposing the cells on a chip and connecting the terminals of the cells by wirings. Accordingly, the integrated circuit having the intended logic function can be fabricated within a short time because logic design can be carried out without taking a circuit operation on a transistor level and layout into consideration.
A “pass transistor circuit” is another technology associated with the present invention. It is known that when the pass transistor circuits are used, logic such as 2-input AND, OR, exclusive-OR (XOR), etc., can be accomplished in a smaller area and at a higher speed than ordinary CMOS circuits by using the same internal circuit connection and changing the application forms of external 2-input signals and their inverted 2-input signals (that is, two complementary input signals).
A publication, J. H. Pasternak et al IEEE Circuits and Devices, July, 1993, pp. 23-28 and a publication K. Yano et al IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 388-395 (1990) can be cited as the references relating to this pass transistor circuit.
These references describe that in order to constitute 3-input OR, AND, XOR, etc., by using the means of this pass transistor circuit, the internal circuit connection for constituting XOR is different from the internal connection for constituting OR and AND, and that the application form of the 3-input signal for constituting XOR is different from the application form of the 3-input signal for constituting OR and AND.
On the other hand, the article “Speed Performance of Pass Transistor Logic Gate Using CMOS/SIMOX Process” by Y. Kado et al, 1992 The Institute of Electronics Information and Communication Engineers of Japan, Spring Meeting, C-560, pp. 5-181 describes a 2-input NAND/AND gate circuit having improved speed performance wherein an inverter for amplifying an output voltage is connected to a source-drain path of a pass transistor, and when the drain and the gate of one pass transistor are driven by complementary input signals or by the same input signal, speed performance can be improved by setting the drain input signal to a ground level Vss or to a power supply voltage level V
DD
.
SUMMARY OF THE INVENTION
When logics of a plurality of cells used in a large-scale logic integrated circuit such as a conventional gate array, a standard cell, etc., are different, the internal circuit connection becomes naturally different.
Therefore, a cell library for accomplishing a large-scale logic integrated circuit generally contains a great number of cells such as sixty or more cells. A great deal of labor are necessary to prepare such a large number of cells. For, it is necessary to determine the internal circuit connection and the positions of the input/output terminals for each of the cells, to execute mask layout and to evaluate a delay time. If the number of cells is reduced so as to reduce this labor, the necessary logics are not prepared as the cells in many cases. In such cases, two or more cells must be combined to accomplish the required logics. As a result, the area of the integrated circuit and its delay time as well as power consumption becomes great. In other words, the reduction of the number of cells registered is not a realistic solution from the aspect of performance.
It is further noteworthy that even when a large number of cells such as at least sixty cells are prepared, only a part of the logic functions practically used can be accomplished. For example, 3-input logics are 256 kinds in all and 4-input logics are as great as 65,536 kinds. Accordingly, even when a simple logic such as 3-input or 4-input is accomplished, the logic function must be practically accomplished by combining a large number of cells of the cell library. The integrated circuit accomplished by the combination of the cells is not always most suitable for the intended logic function, and is inferior to an optimum circuit in every aspects of the speed, the area and power consumption.
The J. H. Pasternak et al reference described above discloses a method of accomplishing logic function, based on standard cells, such as 3-input OR, AND and XOR, using the pass transistor circuit. The standard cell for accomplishing the 2-input and 3-input OR and AND logics accomplished by the present inventors on the basis of the information disclosed in this reference are shown in
FIGS. 5A
to
5
C of the accompanying drawings. In other words, the circuit construction shown in
FIGS. 5A
to
5
C are not known in the art. Since the input of this cell is the 2-input or 3-input, an inverter for signal inversion must be disposed inside the cell. Therefore, a logic circuit for accomplishing the OR or AND logic using the pass transistor can be provided by carrying out in advance layout of the mask pattern such as the source-drain region, the gate electrode, etc., of the transistor of the cell internal or inside circuit shown in FIG.
5
A and then effecting the internal connection of this cell. A simple example is shown in
FIGS. 5B and 5C
.
However, the logic functions accomplished in a cell library shown in
FIG. 5A
is the same as that accomplished in the conventional standard cell library, such as AND and OR. Therefore, the cost of preparing the library is not reduced.
In addition, since the source-drain path of the pass transistor is directly coupled to the output terminal of the cell in this cell, the driving capacity of the cell output is limited by the ON resistance of the pass transistor. Particularly because the source-drain paths of the two pass transistors are connected in series between the input terminal and the output terminal in the 3-input circuit, the driving capacity of this cell output is extremely low.
Because the inverter for inverting the signal must be disposed in this cell, the cell involves the problem that the cell area is great.
In the pass transistor circuits disclosed in the K. Yano et al and Y. Kado et al reference described above, on the other hand, a plurality of complementary input signals are applied, so that the inverter for signal inversion is eliminated inside the circuit, and an inverter for amplifying an output voltage is coupled to the source-drain path of the pass transistor. However, these references do not teach or suggest the concept of using this pass transistor circuit for the cell of the cell library for CAD.
A semiconductor circuit according to an embodiment of the present invention includes a first cell (
31
in
FIG. 3
) and a second cell (
32
in
FIG. 3
) disposed at different positions on a semiconductor chip, wherein:
each of the first and second cells has a substantially square shape and includes first, second, third and fourth active devices (M
13
to M
16
in FIG.
1
), a first node (N
3
)

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