SRAM device using MIS transistors

Details SRAM device using MIS transistors SRAM device using MIS transistors

2002-01-09

2003-08-12

Fahmy, Wael (Department: 2814)

Static information storage and retrieval

Addressing

Multiple port access

C365S051000

Reexamination Certificate

active

06606276

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to SRAM devices and, more particularly, to a 2-port SRAM device (dual-port SRAM device).
Each of Japanese Laid-Open Patent Publications Nos. 10-178110 and 9-270468 discloses the layout of a memory cell composed of six transistors in an SRAM device. In particular, each of the foregoing publications discloses a method for reducing the aspect ratio (which is the ratio of the width of the memory cell in the direction in which a word line extends to the width thereof in the direction in which a bit line extends in the present specification) of the memory cell composed of six transistors shown in
FIG. 7A
, i.e., a method for laying out the cell such that the width thereof in the direction in which the word line extends is larger than the width thereof in the direction in which the bit line extends. Specifically, each of the publications discloses the layout in which P-wells
102
a
and
102
b
are placed on both sides of an N-well
101
to have the N-well
101
interposed therebetween, as shown in FIG.
7
B. In the layout, the six transistors (MN
0
, MN
1
, MN
2
, MN
3
, MPO, and MP
1
) are arranged in generally symmetrical relation relative to the center point of the memory cell.
In the layout of a memory cell
100
shown in FIG.
7
A and
FIG. 7B
, bit lines BL and /BL are disposed on the P-wells
102
a
and
102
b,
respectively. The drive transistors MN
0
and MN
1
each formed of an NMOS are laid out in generally symmetrical relation relative to the center point of the memory cell, as described above, and disposed on the P-wells
102
a
and
102
b,
respectively. Likewise, the access transistors MN
2
and MN
3
each formed of an NMOS are also laid out in generally symmetrical relation relative to the center point P
100
of the memory cell and disposed on the P-wells
102
a
and
102
b,
respectively. The load transistors MP
0
and MP
1
each composed of a PMOS are also laid out in generally symmetrical relation relative to the center point P
100
of the memory cell and disposed on the N-well
101
. The load transistors MP
0
and MP
1
are arranged in two rows parallel to each other and in a direction in which the bit lines extend so that a PMOS region corresponding thereto has a large width (width of the N-well
101
).
A description will be given herein below to the case of laying out a memory cell in a 2-port 8-transistor SRAM device shown in
FIG. 8A
by using the method disclosed in the foregoing publications.
FIG. 8B
shows a memory cell
200
in the 2-port 8-transistor SRAM device that has been laid out by using the technology disclosed in the foregoing publications.
FIG. 9
diagrammatically shows a structure of the bit lines and word lines of the memory cell
200
shown in FIG.
8
B. As indicated by the broken lines, the region shown in FIG.
8
B and
FIG. 9
corresponds to two memory cells (2 bits). The region defined by the broken lines in
FIG. 9
is a memory cell region
200
′ corresponding to the memory cell
200
shown in FIG.
8
B.
As shown in FIG.
8
B and
FIG. 9
, the prior art technology positions P-wells
202
a
and
202
b
on both sides of an N-well
201
such that the N-well
201
is interposed therebetween. For the sake of convenience, two ports will be hereinafter referred to as ports A and B. A pair of bit lines (BLa, /BLa) for the port A are disposed on the P-wells
202
a
and
202
b,
respectively. A pair of bit lines (BLb, /BLb) for the port B are also disposed on the P-wells
202
a
and
202
b,
respectively. Consequently, the eight transistors are arranged in generally symmetrical relation relative to the center point P
200
of the memory cell
200
.
The pair of access transistors (MN
4
, MN
5
) for the port A are disposed on the P-wells
202
a
and
202
b,
respectively. The pair of access transistors (MN
2
, MN
3
) for the port B are also disposed on the P-wells
202
a
and
202
b,
respectively. The load transistors (MP
0
, MP
1
) each formed of a PMOS are arranged in two rows, similarly to the foregoing memory cell
100
, to be laid out in generally symmetrical relation relative to the center point P
200
of the memory cell
200
and disposed on the N-well
201
. The load transistors MP
0
and MP
1
are arranged in two rows parallel to each other and in the direction in which the bit lines extend such that a PMOS region has a large width (width of the N-well
201
).
The ports A and B are normally required to operate completely asynchronously. In the layout of the memory cell
200
shown in
FIG. 8B
, the bit lines BLa and BLb are disposed adjacent to the P-well
202
a
and the bit lines /BLa and /BLb are disposed adjacent to the P-well
202
b.
If the bit lines (BLa, /BLa) for the port A have a read potential difference of several tens of millivolts held therebetween and respective potentials on the bit lines (BLb, /BLb) for the port B vary dynamically to have a write potential difference of 1000 mV or more therebetween, wire-to-wire coupling occurs between the bit lines BLa and BLb disposed adjacent to each other and between the bit lines /BLa and /BLb disposed adjacent to each other. This significantly changes the read potential difference of several tens of millivolts between the bit lines (BLa, /BLa) for the port A and may destroy stored data.
SUMMARY OF THE INVENTION
The present invention has been achieved to solve the foregoing problem and it is therefore an object of the present invention to provide a highly reliable SRAM device.
An SRAM device according to the present invention comprises a memory cell, the memory cell including: a first pair of bit lines connected to a first port; a second pair of bit lines connected to a second port: a first inverter; and a second inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an input terminal of the first inverter, the memory cell having a first region in which an impurity of a first conductivity type is diffused and second and third regions each of a second conductivity type, the second and third regions being adjacent to the first region and opposed to each other with the first region interposed therebetween, the first pair of bit lines being disposed on the second region and the second pair of bit lines being disposed on the third region.
According to the present invention, even if the first and second ports operate completely asynchronously, the influence of wire-to-wire coupling is suppressed or prevented since the first and second ports are disposed physically at a distance from each other.
The first inverter may be composed of first and second MIS transistors, the second inverter may be composed of third and fourth MIS transistors, the memory cell may further comprise: a fifth MIS transistor provided between the output terminal of the first inverter and one of the first pair of bit lines; a sixth MIS transistor provided between the output terminal of the first inverter and one of the second pair of bit lines; a seventh MIS transistor provided between the output terminal of the second inverter and the other of the first pair of bit lines; and an eighth MIS transistor provided between the output terminal of the second inverter and the other of the second pair of bit lines, and the first, second, third, fourth, fifth, sixth, seventh, and eighth MIS transistors may have respective channels oriented in approximately the same direction.
Preferably, the second and fourth MIS transistors are formed on the first region, the first, fifth, and seventh MIS transistors are formed on the second region, the third, sixth, and eighth MIS transistors are formed on the third region, the first and third MIS transistors are disposed in generally symmetrical relation relative to a center point of the memory cell; the fifth and sixth MIS transistor are disposed in generally symmetrical relation relative to the center point of the memory cell, the seventh and eighth MIS transistor are disposed in generally symmetrical relation relative to the center point of the memory cell, a

Affiliated with

Also associated with

Rating

SRAM device using MIS transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM device using MIS transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM device using MIS transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3086422