Power semiconductor device for power integrated circuit device

Details Power semiconductor device for power integrated circuit device Power semiconductor device for power integrated circuit device

2001-04-17

2003-08-05

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S372000

Reexamination Certificate

active

06603176

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a power semiconductor device contained in a power integrated circuit device.
2. Description of the Background Art
A power integrated circuit device (a power IC or HVIC: high voltage IC), in which power semiconductor devices and logical circuits are integrated on one chip, is indispensable to achieve high performance and low cost in the field of mechatronics such as motor control.
Especially in performing bridge rectification of a power line, a P channel LHVMOS (lateral high voltage MOS) transistor and a P channel DAD (dual action device) are usually used for a high side level shift device that transfers a signal (high side signal) sent from a high side (high potential) circuit to a low side (low potential) circuit.
The P channel DAD has such a structure that a P channel LHVMOS transistor and an N channel LHVMOS transistor are integrally formed, and has the characteristic of being able to improve on state current density five times the P channel LHVMOS (Reference material: “An 0.8 &mgr;m High-Voltage IC Using a Newly Designed 600-V Lateral P-Channel Dual-Action Device on SOI”, by K. Watabe et al., IEEE Journal of Solid-state circuits, vol. 33, No. 9, September 1998).
FIG. 30
illustrates a plan configuration of a conventional P channel DAD
900
.
FIG. 31
illustrates a sectional configuration taken along the line A—A in FIG.
30
.
Referring to
FIG. 30
, the P channel DAD
900
has at its midportion a linear source electrode
109
, the periphery of which is surrounded by a first gate electrode
110
. Further, the periphery of the first gate electrode
110
is surrounded by a second drain electrode
113
, second gate electrode
111
and first drain electrode
112
in the order named. Every electrode is of an elongated annulus ring.
A source wiring SL, first gate wiring G
1
, second drain wiring D
2
, second gate wiring G
2
and first drain wiring D
1
are connected to the source electrode
109
, first gate electrode
110
, second drain electrode
112
, second gate electrode
111
and first drain electrode
112
, respectively.
The second drain wiring D
2
is electrically connected via a resistance R
1
to the second gate wiring G
2
, and the second gate wiring G
2
is electrically connected via a resistance R
2
to the first drain wiring D
1
.
Referring now to
FIG. 31
, a sectional configuration of the P channel DAD
900
will be described. The P channel DAD
900
is formed on a SOI substrate in which a buried oxide film
101
and a SOI layer
102
having a relatively low concentration of an N type impurity (i.e., N
−
) are disposed on a support substrate
100
such as a silicon substrate.
Looking from the lefthand of
FIG. 31
, a P type well region
1031
, a P type well region
1032
and an N type well region
104
are disposed in the surface of the SOI layer so that these regions are isolated from one another. Between the P type well region
1032
and N type well region
104
, a P type drain region
107
having a relatively low concentration of a P type impurity (i.e., P
−
) is formed so as to be continuous with the P type well region
1032
. The P type drain region
107
is formed at a shallower position than the P type well region
1032
.
Looking from the lefthand of
FIG. 31
, a P type diffusion region
1051
having a relatively high concentration of a P type impurity (i.e., P
+
) and an N type diffusion region
1061
having a relatively high concentration of an N type impurity (i.e., N
+
) are disposed adjacent each other in the surface of the P well region
1031
. Looking from the righthand of
FIG. 31
, an N type diffusion region
1062
(i.e., N
+
) and a P type diffusion region
1052
(i.e., P
+
) are disposed adjacent each other in the surface of the N type well region
104
.
Disposed on a first main surface of the SOI layer
102
are first and second drain electrodes
112
,
113
and a source electrode
109
. The first drain electrode
112
is formed in contact with the upper surface of the P type diffusion region
1051
and N type diffusion region
1061
in order to cause a short-circuit therebetween. The second drain electrode
113
is formed in contact with the upper surface of the P type well region
1032
. The source electrode
109
is formed in contact with the upper surface of the P type diffusion region
1052
and N type diffusion region
1062
in order to cause a short-circuit therebetween.
As an insulating gate electrode, a first gate electrode
110
is disposed so as to cover the area from the upper surface of the peripheral portion of the P type drain region
107
, the upper surface of the SOI layer
102
(between the P type drain region
107
and N type well region
104
), the upper surface of the N type well region
104
, and to the upper surface of the peripheral portion of the P type diffusion region
1052
. A second gate electrode
111
is disposed so as to cover the area from the upper surface of the peripheral portion of the N type diffusion region
1061
, the upper surface of the P type well region
1031
, the upper surface of the SOI layer
102
(between the P type well region
1031
and P type well region
1032
), and to the upper surface of the peripheral portion of the P type diffusion region
1032
. A gate insulating film GX is present between the SOI layer
102
and the first gate electrode
110
or the second gate electrode
111
.
A back side electrode
114
is formed over the entire surface of a second main surface of the support substrate
100
, and the back side electrode
114
is usually connected to a ground potential.
Description will now be given of operation.
Off state (a forward blocking state) is realized by that the first drain electrode
112
and back side electrode
114
are connected to a ground potential in order to cause a short-circuit therebetween, a power source voltage is applied to the source electrode
109
to obtain a positive potential, and the first gate electrode
110
is connected to the source electrode
109
in order to cause a short-circuit therebetween. Note that the second gate electrode G
2
is free (i.e., no control signal is provided from the exterior) under off state and also on state operation to be described later.
On state is realized by controlling the potential of the first gate electrode
110
to the minus side with respect to the source electrode
109
. That is, by making the potential of the first gate electrode
110
lower than that of the source electrode
109
, a P type channel is formed in the surface of the N type well region
104
and SOI layer
102
which are located immediately below the first gate electrode
110
, and holes are therefore injected from the P type diffusion region
1052
to the P type drain region
107
. This is the same operation as in a usual lateral P channel MOS transistor.
The holes injected to the P type drain region
107
pass through the second drain electrode
113
to the first drain electrode
112
via the resistances R
1
and R
2
. During this, when the potential difference occurred in the resistances R
1
and R
2
becomes a predetermined value, the second gate electrode
111
functions as a gate, and an N type channel is formed in the surface of the P type well region
1031
immediately underlying the second gate electrode
111
.
As a result, electrons are injected from the N type diffusion region
1061
to the SOI layer
102
, and the injected electrons then reach the source electrode
109
via the N type well region
104
and N type diffusion region
1062
. This is the same operation as in a lateral N channel MOS transistor.
Thus, the P channel DAD is a device in which the lateral P channel MOS transistor and the lateral N channel MOS transistor are combined to form a monolithic structure, and has the advantage of reducing on state resistance because the first gate electrode
110
is controlled by a power source side signal (high side signal) and the N channel MOSFET operates in on state.
However,

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