Electronic digital logic circuitry – Security
Reexamination Certificate
2001-05-11
2003-03-18
Le, Don (Department: 2819)
Electronic digital logic circuitry
Security
C326S038000
Reexamination Certificate
active
06535016
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for preventing the unauthorized copying of proprietary application-specific integrated circuit (ASIC) designs. Specifically, a method and circuit is described which when used in designing ASIC circuits produces a circuit whose function has a limited lifetime.
The integrated circuit business includes a significant market for producing custom integrated circuits for various applications. The industry creates these ASIC components through a cooperative venture between the ASIC supplier and the customer who defines a design to be implemented in an ASIC. A course of business has developed between the manufacturer and customer which permits the ASIC design to be implemented using a core circuit defined by the manufacturer, which the customer then adapts to his own proprietary circuit designs. Using a hardware descriptive language, the manufacturer defines a core circuit which the customer will add to his proprietary circuitry. The basic circuit definitions created by the manufacturer are then given to the customer for use in creating the complete ASIC design. The core may be either a hard core, which represents the physical layout of the basic core circuitry around which the customer designs his proprietary circuitry, or a software model, or soft core, which defines the basic circuit of the manufacturer to which the customer adds his proprietary circuitry.
The soft core represents a compilation of a net list which defines the elements and interconnection between elements to carry out a basic circuit function. The compiled net list may be further encrypted by the manufacturer using standard public key encryption methods, and supplied to the user. The user may then encrypt the net list so that it may be further augmented using the hardware descriptive language to define connections between the circuitry and the user's proprietary circuitry. The completed design is returned as an encrypted net list to the manufacturer, who can then create the various masks to implement the ASIC in silicon.
The considerable design effort in these core circuit designs are vulnerable to theft or unauthorized use by other outside manufacturers to implement a customer's ASIC design. The disclosed net list of the core circuitry permits its disclosure to others who may copy the net list, and otherwise take possession of the manufacturer's core designs. The present invention provides the ability to protect a soft core from copying by others, while still permitting the customer to have the ability to modify the soft core in a design which can be manufactured by the legitimate manufacturer.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method to protect ASIC designs from illicit copying.
It is another object of this invention to provide a soft core ASIC design which provides an evaluation capability, but which will not produce a product which functions if produced by the manufacturing process of an unauthorized vendor.
These and other objects of the invention are provided for by a method which protects an ASIC design from illicit copying. The ASIC design begins as a core net list which defines basic circuit functions to be implemented in a silicon substrate. The core net list includes a description of elements within a block for carrying out the circuit function, as well as the interconnection between elements of different blocks having other circuit functions. The net list also includes a circuit which functions to disable the ASIC when the ASIC is implemented in silicon. The circuit which functions to disable the ASIC is distributed among a plurality of the circuit blocks comprising the soft core in order to make its detection and removal difficult for an unauthorized vendor. The manufacturer of the device can remove the disabling function prior to reduction to a silicon component. Illicit copiers, however, not knowing where these components reside within the soft core net list, will not be able to render the design usable by extracting the disabling function.
In accordance with a preferred embodiment of the invention, the net list which defines the soft core for the ASIC includes a timer circuit, which is implemented to disable the ASIC chip after a time out period. The time out period is selected to be greater than the time to evaluate the ASIC design in a simulation facility. However, once the time for simulation has expired, the timer will disable the ASIC, and any additional use of the design, or a component made from the design, will not be possible. In other embodiments of the invention, events which occur in the ASIC circuit occurring after a period of time following a normal simulation and evaluation routine, are used to disable the ASIC.
The components which perform the disabling function are buried within different blocks of the simulation circuit. Thus, an examination of the net list does not readily reveal the location of these components to the user. Accordingly, any attempts to remove the disabling components are very difficult. On the other hand, when the user indicates to the vendor that they want the vendor to manufacturer devices using the defined circuitry, the disabling components may be readily removed from the net list defining the circuit design.
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Choukalos Charles N.
Dean Alvar A.
Tetreault Scott A.
Ventrone Sebastian T.
Connolly Bove & Lodge & Hutz LLP
Le Don
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