Method of making air gaps copper interconnect

Details Method of making air gaps copper interconnect Method of making air gaps copper interconnect

2001-09-28

2003-04-29

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000

Reexamination Certificate

active

06555467

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to inter-level isolation of interconnects in semiconductor devices and more particularly to integration processes for producing very low-k isolation of copper interconnects.
Copper interconnects are formed using a dual damascene process. The incorporation of low-k insulator material may be accomplished by depositing a first layer of low-k dielectric material over a copper interconnect. This may be followed by an optional etch stop barrier insulator and then a second layer of low-k material. A via is then etched through the second layer of low-k material, any etch stop barrier insulator, and the first layer of low-k dielectric material to reach the copper interconnect. A trench is then etched into the second layer of low-k material to aid in forming another layer of copper interconnects. Barrier metal and copper are deposited by sputtering, chemical vapor deposition (CVD), electrochemical deposition, or a combination of these methods. The deposited copper, and possibly the barrier metal, will then be planarized using chemical mechanical polishing (CMP) to form copper interconnects.
Air gaps have been used for intra-level insulators for copper, while using silicon oxide at the inter-level copper layers. The air gaps are formed by decomposing Unity™ sacrificial polymer. However, copper is in direct contact with oxide, which may result in copper diffusion into the oxide causing leakage current flow between adjacent copper lines.
SUMMARY OF THE INVENTION
Accordingly, a method of fabricating copper interconnects to integrate air gaps as inter-level insulator or intra-level and inter-level insulators is provided. A method is provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing. One possible candidate for use as a sacrificial polymer is a copolymer of butylnorbornene and triethoxysilyl norbornene dissolved as a 12wt % solution in mesitylene.
An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a second plurality of metal lines, and at least one via connected to the first metal layer; and an air gap interposed between the first metal layer and the second metal layer. In one embodiment, the air gap is also present between metal lines on either metal layer, such that air gaps act as intra-level as well as inter-level insulators.


REFERENCES:
patent: 6057224 (2000-05-01), Bothra et al.
patent: 6413852 (2002-07-01), Grill et al.
patent: 6423629 (2002-07-01), Ahn et al.
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Georgia Tech Microelectronics Research Center Cleanroom Information, Chemical Index and MSDS Database, http://grover.mirc.gatech.edu/data/msds/index.phtml?type=polymer (Dec. 15, 2002).*
Article entitled, “NURA: A Feasible, Gas-Dielectric Interconnect Process”, by Anand et al., published in VLSI Symposium, Technical Digest, p. 82, 1996.
Article entitled, “Use of Gas as Low-k Interlayer Dielectric in LSI's: Demonstration of Feasibility”, by M. B. Anand et al., published in IEEE ED-44, #11, p. 1965, 1997.
Article entitled, “Air-Gaps in 0.3&mgr;m Electrical Interconnections”, published in IEEE-EDL-21, #12, p. 557, Dec. 2000.

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