Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-01-10
2003-04-15
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S011000
Reexamination Certificate
active
06550020
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing systems and, in particular, to data processing systems having two or more processing cores. Specifically, the present invention relates to a method and system for dynamically configuring a central processing unit with multiple processing cores.
2. Description of the Related Art
Currently, microcomputers are widely utilized in homes and offices as, among other things, word processing devices and Web browsers. Such data processing systems generally utilize a single central processing unit (CPU) embodied in a single microprocessor chip. By contrast, microcomputers designed for more demanding tasks (e.g., network servers) commonly include multiple CPUs. While increasing the number of available processors augments computing power, coordinating the actions of the cooperating CPUs requires a concomitant increase in the complexity of the overall system architecture. For instance, in addition to the central processing units, multi-processor systems typically also include a service processor, the primary duty of which is to prepare the system for operation when the system is powered up or reset (i.e., booted). The service processor typically performs that duty, under the direction of a startup routine, by testing system components, collecting information regarding the system's hardware configuration, and then passing control to one of the CPUs for initiation of the operating system and completion of the boot procedure.
Due to recent advances in the manufacture of integrated circuits, however, multi-core microprocessor chips may soon be replacing single-core CPUs as the processor of choice for high-performance microcomputers. Multi-core microprocessors feature a single integrated circuit that includes two or more main processing cores, each of which may be utilized as if it was a separate central processing unit. Furthermore, in state-of-the-art multi-core processors, each of the main cores provides computing power that equals or exceeds that of a conventional high-performance single core processor.
Among the benefits provided by multi-core processors is an increase in physical processing core hdensity within multiprocessor data processing systems, in that more processing cores may operate within a given amount of space, which leads to improvements in overall multiprocessor system performance. A problem associated with multi-core CPUs, however, is that they require additional complexity be introduced into the areas of production testing, boot testing, and system operation. Also, multi-core processors are physically larger and more complex than single-core processors and are therefore more likely to suffer from production defects. However, conventional multi-core data processing systems lack effective means for addressing these problems.
Therefore, as recognized by the present invention, a need exists for methods and systems that reduce the complications associated with testing and utilizing multi-core CPUs. As the present invention also recognizes, there exists a need to provide flexibility with regard to configuring multi-core processors. For example, production yields could be increased if a multi-core CPU with a production defect in a first core (but not a second) could be configured so that the second core operates as if it is the first. Also, it would be beneficial to allow processing power to be augmented and malfunctioning processing cores to be replaced and/or eliminated without shutting down a system or otherwise interrupting system operation. It would also be advantageous to allow engineering code, testing code, and startup routines to be written without regard to many of the numerous details associated with utilizing one processing core to emulate another, and to allows such programs. Furthermore, it would be beneficial if engineering code, testing code, and startup routines that were designed for single-core multiprocessor machines or for fully populated multi-core multiprocessor machines could be utilized, with little or no modification, in systems with partially good or partially inactive multi-core processors. As described below, the present invention provides these and other benefits.
SUMMARY OF THE INVENTION
A data processing system according to the present invention has at least one integrated circuit containing a central processing unit (CPU) that includes at least first and second processing cores. The integrated circuit also includes input facilities that receive control input specifying which of the processing cores is to be utilized. In addition, the integrated circuit includes configuration logic that decodes the control input and, in response, selectively controls reception of input signals and transmission of output signals of one or more of the processing cores in accordance with the control input. In an illustrative embodiment, the configuration logic is partial-good logic that configures the integrated circuit to utilize the second processing core, in lieu of a defective or inactive first processing core, as a virtual first processing core.
All objects, features, and -advantages of the present invention will become apparent in the following detailed written description.
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Geisinger, Patrick P. Microprocessor for the New Milennium: Challenges, Opportunities, and New Frontiers. 2001, IEEE Internation Solid State Circuits Conference. pp. 21-25.
Floyd Michael Stephen
Reick Kevin F.
Skergan Timothy M.
Bonura Timothy M.
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Iqbal Nadeem
Salys Casimer K.
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