Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-10-25
2003-07-22
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S230060, C365S189090
Reexamination Certificate
active
06597610
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to digital memory systems and more particularly to a system and method for providing stability for a low power static random access memory cell.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Integrated circuits are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, integrated circuits are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Integrated circuits may include transistors, capacitors, resistors and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers and other components of an integrated circuit. One type of memory array is a static random access memory (SRAM) in which memory cells are continuously available for reading and writing data. As technology improves, SRAM cells and other components are designed to operate at lower supply voltages.
In some SRAM cells, high threshold voltage n-channel transistors are used to ensure data retention. However, for SRAM cells operating at relatively low supply voltages, using high threshold voltage n-channel transistors may result in the SRAM cells becoming unstable during a read operation.
SUMMARY OF THE INVENTION
In accordance with the present invention, a system and method for providing stability for a low power static random access memory (SRAM) cell are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides an SRAM cell with high threshold voltage n-channel transistors to ensure data retention and a limited wordline voltage swing to ensure stability during read operations.
In one embodiment of the present invention, a system for providing stability for a low power SRAM cell is provided that includes a wordline, a driver and a mode selector. The wordline is coupled to the SRAM cell. The wordline is operable to select the SRAM cell for read and write operations when activated and to de-select the SRAM cell when de-activated. The driver is coupled to the wordline. The driver is operable to activate and de-activate the wordline. The mode selector is coupled to the driver. The mode selector is operable to provide a mode signal to the driver to place the wordline into one of a plurality of modes.
In another embodiment of the present invention, a method for providing stability for a low power SRAM cell is provided. A wordline is coupled to the SRAM cell. The wordline is operable to select the SRAM cell for read and write operations when activated and to de-select the SRAM cell when de-activated. A driver is coupled to the wordline. The driver is operable to activate and de-activate the wordline. A mode selection is received for the wordline. A mode signal is provided to the driver based on the received mode selection. The wordline is placed into one of a plurality of modes based on the mode signal.
In yet another embodiment of the present invention, a method for providing stability for a low power SRAM cell is provided. A wordline is coupled to the SRAM cell. The wordline is operable to select the SRAM cell for read and write operations when activated and to deselect the SRAM cell when de-activated. A driver is coupled to the wordline. The driver is operable to activate and de-activate the wordline. A stability level is monitored for the SRAM cell. A mode signal is provided to the driver based on the stability level for the SRAM cell. The wordline is placed into one of a plurality of modes based on the mode signal.
Technical advantages of the present invention include providing an improved low power SRAM cell. In a particular embodiment, the SRAM cell includes high threshold voltage n-channel transistors, in addition to a wordline driver that is operable to limit the wordline voltage swing during low power operating conditions and allow a full wordline voltage swing otherwise. As a result, data retention and stability during read operations are ensured for the SRAM cell during low power operating conditions, while performance during normal operating conditions is unaffected. Accordingly, the SRAM cell functions properly under low power testing conditions, as well as under normal operating conditions.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5396464 (1995-03-01), Slemmer
patent: 5450362 (1995-09-01), Matsuzaki
Brady III Wade James
Lam David
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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