Depletion mode SCR for low capacitance ESD input protection

Details Depletion mode SCR for low capacitance ESD input protection Depletion mode SCR for low capacitance ESD input protection

2002-03-04

2003-08-26

Pham, Long (Department: 2814)

Chemistry of inorganic compounds

Treating mixture to obtain metal containing compound

Alkali metal

C257S355000

Reexamination Certificate

active

06610262

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to the structure and manufacturing process of a FET semiconductor device for ESD protection of electronic circuit devices and more particularly to a depletion mode SCR for low capacitance input ESD protection particularly suited to high frequency applications.
(2) Description of Prior Art
Because of high input impedance and thin oxide gate structures, the problem of electrostatic discharge damage (ESD) with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pads usually have a protective device connected between the I/O pad and the internal circuits which allows the ESD current to be shunted to ground, protecting the active internal circuits from damage.
With prior art devices, the capacitance associated with the ESD protection device on the active circuit input pad can be in the order of 0.27 picofarads (pF) or greater. This capacitance is caused to a large degree by the N-well-P-substrate junction capacitance. For some logic operation application speeds, this capacitance may be acceptable. However, in high frequency applications such as radio frequency (RF) or other applications in the megahertz to gigahertz range, the input capacitance should be minimized as much as possible to avoid circuit performance degradation.
In the “Prior Art” as shown in
FIG. 1
the active circuit signal input pad
108
is electrically connected to a P+ contact
320
of a N-well
180
that resides within a P substrate
100
. The input pad is also electrically connected to the N+ drain
241
of NFET
1
and N+ drain
242
of NFET
2
. NFET
1
source
261
and NFET
2
source
262
are electrically connected to a second voltage source, typically ground as shown in FIG.
1
. The P substrate
100
is also connected to the second voltage, or ground, through the P+ substrate contacts
300
. Depicted are the parasitic bipolar PNP transistors T
11
and T
12
, and the parasitic bipolar NPN transistors T
13
, T
14
, T
15
, T
16
, and resistors R
11
, R
12
, R
13
, R
14
which exist within the structure. Also shown is diode D
11
. Parasitic bipolar transistors T
11
and T
13
effectively function as a PNPN SCR device as do a parasitic transistors T
12
and T
14
.
An ESD incident pulse will propagate through D
11
and the base collector junction of T
11
and
12
turning on T
13
, T
14
T
15
and Tl
6
, shunting the ESD current to ground. The circuit has appropriate feedback to maintain the shunted current flow until the ESD event is terminated. The device does offer ESD protection, but there is a large capacitance of approximately 0.27 pF associated with this prior art design. As previously mentioned, the capacitance comes primarily from the N well
300
to P substrate
100
junction as well as from the N+ NFET drain
241
and the P substrate
100
junction. This level of capacitance on the input circuit of an RF device can be detrimental to circuit high frequency performance. The invention provides a novel and unique structure and process that provides effective ESD protection while reducing the device capacitance by a nominal order of magnitude to the range of 0.02 to 0.03 pF.
The following patents and reports pertain to ESD protection.
U.S. Pat. No. 5.537,284 (Haas, Jr. et al.) Electrostatic Discharge Protection Device
U.S. Pat. No. 5,821,572 (Walker et al.) Simple BICMOS Process for Creation of Low Trigger Voltage SCR and Zener Diode Protection
U.S. Pat. No. 5,825,600 (Watt) Fast Turn-On Silicon Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) Protection
U.S. Pat. No. 6,074,899 (Voldman) 3-D CAMOS-ON-Soi ESD Structure and Method
The following technical reports also refer to the subject of ESD protection in MOS circuits
Wu et al., “ESD) Protection for output Pad with Well-Coupled Field-Oxide Device in 0.5 m CMOS Technology,” IEEE Transactions on Electron Devices, Vol. 44, No. 3, March 1997, IEEE
Ker et al., “ESD Protection Design on Analog Pin with Very Low Input Capacitance for High-Frequency or Current-Mode Applications, “IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, August 2000, IEEE
Kleveland et al., “Distributed ESD Protection for High-Speed Integrated Circuits,” IEEE Electron Device Letters, Vol. 21, No. 8, August 2000, IEEE
SUMMARY OF THE INVENTION
Accordingly, it is the primary objective of the invention to provide an effective and manufacturable method and structure for reducing the capacitance of the protective device providing resistance to the potential damage caused by the phenomenon known as electrostatic discharge (ESD) by utilizing a low capacitance depletion mode SCR connected to an input pad of an integrated circuit device.
It is a further objective of the invention to improve ESD protection for high frequency and radio frequency (RF) applications by providing a low input capacitance structure that will have minimum impact on device performance while maintaining reasonable ESD protection levels.
A still additional objective of the invention is to provide the ESD protection with reduced capacitance without changing the characteristics of the internal circuits being protected and by using a process compatible with the process of integrated MOS device manufacturing.
The above objectives are achieved in accordance with the methods of the invention that describes a structure and a manufacturing process for semiconductor ESD protection devices with reduced input capacitance. A heavily doped P+ contact area residing in an N well region is connected to the input pad of active integrated field effect transistors (FETs). N-channel field effect transistor (NFET) N+ drain areas located adjacent to and on either side of the N-well within the P substrate body, as are the NFET N+ source regions and P+ substrate contact areas.
A unique feature of the invention is that it utilizes shallow trench isolation (STI) elements to reduce the NFET drains to substrate junction capacitance, and the N-well and associated P+ contact junction capacitance. This isolation elements are locate between the N-well P+ contact region and the NFET N+ drain regions and straddle the N-well to substrate junction boundary in the surface region. These STI elements have the effect of reducing the N+ drain to substrate boundary area, as well as N well to P substrate boundary area with a subsequent reduction in the input capacitance. In addition, the invention allows the NET gates and drains to be electrically floating which further reduces the capacitance on the input pad.
A voltage pulse from an ESD event will cause the parasitic bipolar transistors that effectively form a SCR device structure to trigger providing a path to ground for the ESD current, thereby protecting the internal circuits from damage.


REFERENCES:
patent: 5537284 (1996-07-01), Haas, Jr. et al.
patent: 5821572 (1998-10-01), Walker et al.
patent: 5825600 (1998-10-01), Watt
patent: 5950098 (1999-09-01), Oda et al.
patent: 6074899 (2000-06-01), Voldman
patent: 6333528 (2001-12-01), Arita et al.
patent: 6344385 (2002-02-01), Jun et al.
Wu et al., “ESD Protection for Output Pad with Well-Coupled Field-Oxide Device in 0.5um CMOS Technology,” IEEE Transactions on Electron Devices, vol. 44, No. 3, Mar. 1997, IEEE.
Ker et al., “ESD Protection Design on Analog Pin with Very Low Input Capacitance for High-Frequency or Current-Mode Applications,” IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000, IEEE.
Kleveland et al., “Distributed ESD Protection for High-Speed Integrated Circuits,” IEEE Electron Device Letters, vol. 21, No. 8, Aug. 2000, IEEE.

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