Semiconductor memory device and control method thereof

Details Semiconductor memory device and control method thereof Semiconductor memory device and control method thereof

2001-10-23

2003-05-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S203000, C365S206000

Reexamination Certificate

active

06567298

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to data storage in memory cells in a semiconductor memory device, and more particularly to charge retention in a semiconductor memory device which has cell capacitors for storing charge in memory cells and stores data by storing charge.
2. Description of Related Art
A random access memory (hereinafter referred to as a “DRAM”) has been conventionally used as a typical example of a memory device which has a cell capacitor for storing charge in a memory cell.
FIG. 15
is a circuit block diagram showing a DRAM
1000
as an example of a semiconductor memory device according to a conventional art. A semiconductor memory device such as the DRAM
1000
is configured such that memory cells COO to Cnm arranged in a matrix shape are divided into multiple cell blocks B
1
to Bk. Each of the cell blocks B
1
to Bk has a similar configuration. Hereinafter, the cell block B
1
will be described as an example of the cell block. Word lines WL
0
to WLn for selecting the memory cells C
00
to Cnm by each line address are connected to the memory cells C
00
to Cnm. Stored charge in the selected memory cells C
00
to Cnm is read out onto bit lines BL
0
, /BL
0
to BLm, /BLm as data transfer passages. The bit lines BL
0
, /BL
0
to BLm, /BLm are connected to sense amplifier circuits (not illustrated) provided in a sense amplifier group
102
and the read-out stored charge is differentially amplified on a bit line pair. In a recent large-capacity DRAM
1000
, sense amplifier circuits are generally configured between a ground potential GND and a power supply Viic whose voltage is stepped down by an internal step-down power supply.
The memory cells C
00
to Cnm corresponding to the bit line pairs BL
0
and /BL
0
to BLm and /BLm are paired to constitute a memory cell unit U (see FIG.
17
). Each of the bit line pairs BL
0
and /BL
0
to BLm and /BLm is provided with a sense amplifier circuit. Drivers for driving the word lines WL
0
to WLn are configured for each row address as a word driver group
101
.
The stored charge retained by the memory cells C
00
to Cnm selected by the word lines WL
0
to WLn is read out onto the bit lines BL
0
to /BLm, and is differentially amplified and read out as data by the sense amplifier circuits, or the stored charge in the memory cells C
00
to Cnm is refreshed. Consequently, it is necessary to reset (hereinafter referred to as “equalize”) the bit line pairs BL
0
and /BL
0
to BLm and /BLm at each access cycle in preparation for the next access. Therefore, the bit line pairs are equalized by a bit line equalization group
106
at the end of access (hereinafter referred to as “at the time of pre-charge”).
At the time of equalization, all bit lines BL
0
to /BLm belonging to the cell block B
1
are short-circuited with each other by a transistor (not illustrated) provided in the bit line equalization group
106
. Then, the bit lines are equalized to a reference voltage VPR by a reference voltage generation circuit
104
. The bit line pairs which are differentially amplified by the internal step-down voltage Viic are equalized. Therefore, the voltage of the bit lines becomes Viic/2 and the reference voltage VPR is also set at Viic/2. Since many bit lines BL
0
to /BLm exist in the cell block B
1
, the sum of the parasitic capacitances of all bit lines at the time of equalization has a significant capacitance value. The sum of the parasitic capacitances of all bit lines at the time of equalization is shown as the bit line equalization capacitance CPR in FIG.
15
.
On the other hand, the potential of a cell plate CP
1
for cell capacitors (C
0
, Cl in
FIG. 17
) for storing charge in the memory cells C
00
to Cnm is also biased to the reference voltage VCP by the reference voltage generation circuit
104
. Since the differentially amplified voltage is the voltage Viic also at this location, the reference voltage VCP is generally set at Viic/2 to minimize an electric field applied to the cell capacitors C
0
, C
1
. In other words, the reference voltage output from the reference voltage generation circuit
104
is Viic/2. Since the cell plate CP
1
is common to all memory cells C
00
to Cnm belonging to the cell block B
1
, the parasitic capacitance has a significant capacitance value. The sum of the parasitic capacitances is shown as the cell plate parasitic capacitance CCP in FIG.
15
.
The reference voltages VPR, VCP are supplied to each of the cell blocks B
1
to Bk by lines VPR, VCP through NMOS transistors MPR, MCP. In the large-capacity DRAM
1000
, the area where the cell blocks B
1
to Bk are arranged is large. Therefore, the total wiring length of each of the feeders (the lines VPR, VCP) are large and parasitic resistances RPR
0
to RPRk, RCP
0
to RCPk exist on the wiring paths.
The lines VPR, VCP are separated from the reference voltage generation circuit
104
by control signals &phgr;PR, &phgr;CP supplied to the NMOS transistors MPR, MCP. A bias can be externally applied through test pads PCP, PPR.
In addition, the recent large-capacity DRAM or the like is sometimes configured such that dummy capacitors DC
00
to DC
1
m
are interposed between dummy word lines DWL
0
, DWL
1
and the bit lines BL
0
to /BLm. Owing to this configuration, the dummy word lines DWL
0
, DWL
1
are simultaneously driven by a dummy word driver group
103
at the time of access and charge is supplied supplementarily to the bit lines BL
0
to /BLm by using the capacitive coupling effect by the dummy capacitors DC
00
to DC
1
m
, thereby improving the margin of stored charge read out from the memory cells C
00
to Cnm. An operation for improving the read-out characteristics with regard to information “1” is called assist 1, and an operation for improving the read-out characteristics with regard to information “0” is called assist 0.
An example of a reference voltage generation circuit
104
is shown in FIG.
16
. The reference voltage generation circuit
104
is constituted by a reference voltage generation portion
104
B and a reference voltage drive portion
104
D. In the reference voltage generation portion
104
B, the source terminal of a diode-connection type NMOS transistor M
7
connected to power supply voltage VDD through a PMOS transistor M
6
, and the source terminal of a diode-connection type PMOS transistor M
8
connected to a ground potential GND through an NMOS transistor M
9
are connected with each other. Owing to this configuration, the drain terminals of the transistors M
7
, M
8
output a constant bias voltage independently of the power supply voltage VDD. This bias voltage is input to the gate terminals of an NMOS transistor M
10
and a PMOS transistor M
11
constituting the reference voltage drive portion
104
D. A connection is made between the source terminals of the transistors M
10
, M
11
to constitute an output terminal. Each of the transistors M
10
, M
11
functions as a source follower to keep the voltage of the output terminal at a reference voltage. Resistance devices R
1
, R
2
may be connected to the output terminal as compensating devices.
FIG. 17
shows the memory cell unit U (see FIG.
15
). The memory cell unit U is composed of a pair of memory cells C
00
, C
10
. In each of the memory cells C
00
, C
10
, cell capacitors C
0
, C
1
are connected to bit lines BL
0
, /BL
0
through NMOS transistors M
0
, M
1
controlled by word lines WL
0
, WL
1
. In general, the NMOS transistors M
0
, M
1
are called transfer gates. Stored charge is given and received via the NMOS transistors M
0
, M
1
as the transfer gates between charge storage nodes ST
0
, ST
1
which are terminals on one side of the cell capacitors C
0
, C
1
and the bit lines BL
0
, /BL
0
to store data. The terminals on the other side of the cell capacitors C
0
, C
1
are connected to a common cell plate CP
1
, and the potential of the cell plate CP
1
is biased to the reference voltage VCP by the reference voltage generation circuit
104
. Since the potential of the cell plate CP
1
is the reference voltage for st

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