Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1996-03-06
2003-08-19
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000
Reexamination Certificate
active
06607947
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a thin-film transistor (from here on will also be referred to as a TFT) which is made of non-single-crystal semiconductor, for example an IG-FET, and its manufacturing process, and in more particular, to a highly reliable thin-film transistor which is suitable for use as a driving element of a display image sensor or liquid crystal device or the like.
Thin-film transistors can be formed by a chemical vapor deposition method on an insulated substrate in a comparatively low temperature atmosphere, with a maximum temperature of 500° C., and the substrate being made of an inexpensive material such as soda glass or boron-silicate glass.
This thin-film transistor is a field-effect transistor and has the same features as a MOSFET. In addition, as mentioned above, it has the advantage that it can be formed on an inexpensive insulated substrate at a low temperature. Also the thin film transistors can be formed on a large substrate by the use of CVD techniques. It is therefore a very good prospect for use as switching elements of a matrix type liquid crystal display having a lot of picture elements, or as switching elements of a one-dimensional or two-dimensional image sensor.
Also, the thin-film transistors can be formed using already established photolithography technology, by which a very minute process is possible, and transistors can be integrated just as making an IC and so on.
FIG. 1
shows the construction of a typical prior art TFT.
In
FIG. 1
, the thin-film transistor is comprised of an insulated substrate
20
made of glass, a semiconductor thin film
21
made of a non-single-crystal semiconductor, a source
22
, a drain
23
, a source electrode
24
, a drain electrode
25
, gate insulating film
26
, and a gate electrode
27
.
In this type of thin-film transistor, the current flow between the source
22
and the drain
23
is controlled by applying a voltage to the gate electrode
27
. The response speed of the thin-film transistor is given by the equation;
S=&mgr;·V/L
2
where L is a channel length, &mgr; is a carrier mobility, and V is the gate voltage.
In this type of thin-film transistor, the non-single-crystal semiconductor layer contains many grain boundaries. The non-single-crystal semiconductor, when compared to the single-crystal semiconductor, has disadvantages that the carrier mobility is very low and thus the response speed of the transistor is very slow due to the many grain boundaries. Especially if an amorphous silicon semiconductor is used, the mobility is only about 0.1−1 (cm
2
/V.sec) and is too short to function for use as a TFT.
It is obvious that to solve this problem the channel length needs to be shortened and the carrier mobility increased. Many improvements are being made.
When the channel length L is decreased, the effect it has on the response speed is as the square of the length, and so it is a very effective means. However, when forming elements on a large area substrate, it is apparently difficult to use the photolithography technique in order that the space between the source and drain (this is essentially the channel length) should 10 &mgr;m or less, due to the precise process, yield, and manufacturing cost problems. Consequently, effective means for shortening the channel length of the TFT have not been found.
On the other hand, to increase the mobility (&mgr;) of the semiconductor layer, single-crystal semiconductor or poly-crystal semiconductor material is used, and when using amorphous semiconductor material, after the semiconductor is formed, the active region of the TFT should be crystallized using a process such as heat treatment.
In this case, a temperature higher than what is normally required to form a-Si is necessary. For example;
(1) For a thin-film transistor made of amorphous semiconductor material, the amorphous silicon film is made at a temperature of about 250° C. and then a maximum temperature of 400° C. is required for thermal annealing.
(2) When a poly-crystal silicon film is formed by a low pressure CVD method, the maximum temperature required for forming the film and then for recrystallization is 500 to 650° C.
(3) For a thin-film transistor where only an active layer is converted to a poly-crystalline structure, the required CVD temperature for forming the semiconductor layer is 250 to 450° C., however the temperature exceeds 600° C. during a recrystallization step of the active layer by CW laser.
The TFT is formed on a substrate made of a material such as soda glass and the active region comes in direct contact with the glass substrate, especially in the case of stagger-type and coplanar-type transistors. When making a TFT that has sufficiently fast response speed, the heat treatment mentioned above is necessary, and so the metallic alkali impurities such as sodium and potassium which exist in the glass substrate are externally diffused and forced into the semiconductor layer which forms the active layer or TFT. This lowers the mobility of the semiconductor layer and changes the threshold value, making the characteristics of the device worse and has an adverse effect on the long-term reliability of the device.
Also, through operation of the TFT, the TFT produces heat which causes the temperature of the glass substrate to rise thus causing impurities to be diffused from the substrate, which also has an adverse effect on the TFT.
Generally, a gate-insulator of the IG-FET is made of a silicon oxide film which is formed by a sputtering method with argon (Ar) gas used as a sputtering gas. In the sputtering process, the argon atoms are inherently introduced into the gate insulator and generate a fixed charge in the semiconductor film. Also, ions that exist in a reaction space during the sputtering collide with the surface of the active layer of the thin-film transistor, which causes a damage to the active layer. As a result, a mixed layer of the active layer and the insulation layer is formed in the boundary region of the gate insulation layer and the active layer of the transistor. In producing a TFT as described above, the problems of response speed and reliability need to be solved.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to produce a high speed TFT which uses non-single-crystal semiconductor. It is another object of the present invention to solve the problem of reliability mentioned above.
In order to solve the above problems, in this invention an insulation layer 500 Å to 5000 Å thick is formed on the glass substrate as a bottom protective film before the TFT elements are formed, and the TFT elements are formed on top of this protective film. In this structure, it is possible to keep the impurities existing in the glass substrate from going into the active layer of a thin-film transistor or into the transistor elements themselves, and to provide a thin-film transistor that has high mutual conductance and high field-effect mobility. Also it suppresses the diffusion of impurities from the substrate which occurs when heat is generated during operation of the device. It also provides a thin-film transistor that can control degeneration of the electrical characteristics and has long-term stability and reliability.
Also by adding a halogen element to the protective film or to the gate insulator, impurities intruded from the outside or impurities in the film can be neutralized. Interface states between the insulation layer and the semiconductor layer can also be reduced by the halogen element. This increases stability and reliability of the TFT.
REFERENCES:
patent: 3933530 (1976-01-01), Mueller et al.
patent: 4027380 (1977-06-01), Deal et al.
patent: 4217194 (1980-08-01), Lübers et al.
patent: 4330363 (1982-05-01), Biegesen et al.
patent: 4377421 (1983-03-01), Wada et al.
patent: 4403239 (1983-09-01), Yamazaki
patent: 4404735 (1983-09-01), Sakurai
patent: 4451838 (1984-05-01), Yamazaki
patent: 4459739 (1984-07-01), Sheperd et al.
patent: 4502204 (1985-03-01), Togashi et al.
patent: 4517733 (1985-05-01), H
Yamazaki Shunpei
Zhang Hongyong
Costellia Jeffrey L.
Nixon & Peabody LLP
Pert Evan
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Method of manufacturing a semiconductor device with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3083104