Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-08
2003-04-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S771000, C438S776000
Reexamination Certificate
active
06551914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a structure in which an interconnection is buried in an opening formed in an interlevel insulating film and, more particularly, to a semiconductor device in which damage to an interlevel insulating film is prevented to increase the manufacturing yield, and a method of manufacturing the same.
2. Description of the Prior Art
With recent high integration degrees of semiconductor devices, micropatterning of interconnections is demanded. For such a fine interconnection, contact and through holes for connecting conductive layers or interconnections respectively formed on the upper and lower surfaces of an interlevel insulating film must be particularly small. For this purpose, the structure of a contact or through hole in which an opening reaching a lower conductive layer or interconnection is formed in an interlevel insulating film, and an interconnection material is buried in this opening is proposed. For example, according to the technique disclosed in Japanese Unexamined Patent Publication No. 5-275366, as shown in
FIG. 1A
, a first metal interconnection
12
on a semiconductor substrate
11
is covered with an interlevel insulating film
13
, then a via hole
14
is formed in the interlevel insulating film
13
, and a tungsten film
15
is formed on the entire surface including the via hole
14
. The tungsten film
15
is polished by chemical mechanical polishing (to be referred to as CMP hereinafter) until the tungsten film
15
on the surface of the interlevel insulating film
13
is removed. As a result, the tungsten film
15
is left only in the via hole
14
. A plug (through hole) is formed in this manner, and permits one to electrically connect the first metal interconnection
12
to a second metal interconnection
16
to be formed.
Since the plug structure using CMP has high flatness on the surface of the interlevel insulating film
13
, the coverage of the second upper metal interconnection
16
is high, and so-called poor step coverage and the like can be prevented, which is advantageous in micropatterning the interconnection. In this CMP, however, if the tungsten film
15
is excessively polished, the surface of the interlevel insulating film
13
is also polished and may be scratched. That is, a slurry of alumina particles is used as an abrasive in polishing the tungsten insulating film
13
along with the progress of the polishing, scratches
13
a
are generated on the surface of the interlevel insulating film
13
by hard alumina particles, as shown in FIG.
1
B.
The generation of scratches adversely affects the cladding of the second metal interconnection
16
formed on the surface of the interlevel insulating film
13
, pattern etching, and the like. Consequently, the reliability of the resultant semiconductor device decreases, and the manufacturing yield also greatly decreases.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation in the prior art, and has as its object to provide a semiconductor device and manufacturing method in which the surface of an interlevel insulating film is prevented from being scratched in a CMP process, thereby increasing the reliability and the yield.
To achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor device in which an interconnection material is buried in a hole formed in an interlevel insulating film arranged on a semiconductor substrate, comprising a protective layer formed on a surface of the interlevel insulating film that has a lower polishing rate than a polishing rate of the interconnection material in chemical mechanical polishing.
According to the second aspect of the present invention, there is provided a semiconductor device wherein the protective layer in the first aspect has a polishing rate ratio of not less than 10 to the interconnection material in chemical mechanical polishing.
According to the third aspect of the present invention, there is provided a semiconductor device wherein the protective layer in the first aspect is a reaction layer formed by performing, for the surface of the interlevel insulating film, plasma processing using at least one kind of gas selected from the group consisting of NH
3
gas and N
2
gas.
According to the fourth aspect of the present invention, there is provided a semiconductor device wherein the protective layer in the second aspect is a plasma oxide film formed on the surface of the interlevel insulating film.
According to the fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming an interlevel insulating film on a semiconductor substrate, forming a protective layer with a low polishing rate in chemical mechanical polishing on a surface of the interlevel insulating film, forming a hole in the interlevel insulating film, forming an interconnection material on the surface of the interlevel insulating film including the hole, and forming an interconnection by chemically mechanically polishing the interconnection material so as to leave the interconnection material in only the hole.
According to the sixth aspect of the present invention, there is provided a semiconductor device manufacturing method wherein the protective layer in the fifth aspect is a reaction layer formed by performing, for the surface of the interlevel insulating film, plasma processing using at least one kind of gas selected from the group consisting of NH
3
gas and N
2
gas.
According to the seventh aspect of the present invention, there is provided a semiconductor device manufacturing method, further comprising the step of forming, as the protective layer in the fifth aspect, a plasma oxide film having a polishing rate ratio of not less than 10 to the interconnection material in chemical mechanical polishing.
As is apparent from the respective aspects, according to the present invention, the plasma processing layer or plasma oxide film is formed as a protective layer on the surface of the interlevel insulating film by plasma processing using NH
3
gas or N
2
gas. In polishing by CMP the interconnection material formed on the interlevel insulating film, the protective film protects the surface of the interlevel insulating film to prevent this surface from being scratched. With this structure, an upper interconnection layer and an insulating film can be formed with high quality, and high reliability and high manufacturing yield of the semiconductor device can be obtained.
The above and many other advantages, features and additional objects of the present invention will become manifest to those versed in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principles of the present invention are shown by way of illustrative examples.
REFERENCES:
patent: 5592024 (1997-01-01), Aoyama et al.
patent: 5821168 (1998-10-01), Jain
patent: 5886410 (1999-03-01), Chiang et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5916011 (1999-06-01), Kim et al.
patent: 6004729 (1999-12-01), Bae et al.
Wolf, Silicon Processing for the VLSI Era, 1990, Lattice Press, vol. 2, 194-198.*
Chang et al, ULSI Technology, 1996, McGraw-Hill Companies, Inc., 244-248.
Kubo Akira
Suzuki Mieko
Hayes & Soloway P.C.
Lytle Craig P.
NEC Electronics Corporation
Smith Matthew
LandOfFree
Method of forming polish stop by plasma treatment for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming polish stop by plasma treatment for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming polish stop by plasma treatment for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3082351