Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-04
2003-04-15
Callahan, Timothy P. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C257S359000, C257S360000
Reexamination Certificate
active
06550039
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus of circuit design for designing integrated circuit devices, and more particularly to a method and an apparatus of circuit design for designing conductive members connected to a gate insulating film of a transistor element to have antenna sizes of proper values in design of an integrated circuit device including the conductive members.
2. Description of the Related Art
Integrated circuit devices are currently used in various types of electronic equipment. Such an integrated circuit device has various circuit elements such as transistors formed therein with a thin-film technology. A transistor element formed in an integrated circuit device with the thin-film technology has a gate insulating film connected to conductive members such as a gate electrode, metal wiring and the like.
For example, in integrated circuit device
1
in the process of manufacture illustrated in
FIG. 1
, gate electrode
4
and metal wiring
5
are connected as conductive members to gate insulating film
3
of transistor element
2
, and metal wiring
5
is located on the upper surface of insulating layer
6
which is an insulating member. Photoresist
7
which is an insulating member is temporarily deposited as a mask on the upper surface of metal wiring
5
. Metal wiring
5
is processed through plasma anisotropic etching which uses photoresist
7
as a mask.
In integrated circuit device
1
as mentioned above, when metal wiring
5
is subjected to the anisotropic etching, the exposed side surface of metal wiring
5
is exposed to plasma and may receive electric charges in the plasma. Since the electric charge received by metal wiring
5
flows from gate electrode
4
to semiconductor substrate
8
through gate insulating film
3
, gate insulating film
3
may be damaged.
The presence or absence of the damage depends on the density of the electric charges flowing through gate insulating film
3
, and the density of the electric charge depends on the intensity of the plasma, the area of gate insulating film
3
, and the antenna size of metal wiring
5
. In other words, if the intensity of the plasma used in the manufacturing process is known, only the area of gate insulating film
3
and the antenna size of metal wiring
5
may be taken into consideration in design.
Conventionally, maximum antenna size M
0
of a conductive member permissible with respect to reference area S
0
of a gate insulating film is defined, and the ratio of them is represented as maximum permissible antenna ratio R
0
by:
R
0
=M
0
/S
0
When a new gate insulating film with area Sj is actually formed, damage to the gate insulating film can be prevented by setting antenna size Mi of an actual conductive member connected to the gate insulating film in accordance with:
Mi≦R
0
×
Sj
The antenna size of a conductive member refers to the size of the portion of the conductive member serving as an antenna, for example the area of the exposed portion of the metal wiring as mentioned above. When reference metal wiring has the same film thickness as that of new metal wiring, the antenna size thereof can be approximately represented by the area of the upper surface of the metal wiring if only the upper surface of the metal wiring is exposed, or if only the side surface of the metal wiring is exposed, the antenna size can be approximately represented by the overall length of the perimeter of the metal wiring.
In an actual integrated circuit device, as shown in
FIG. 2
, a multilayered structure including a plurality of conductive members may be connected to a single gate insulating film such that each of the conductive members serves as an antenna. In such a case, each of the plurality of conductive members is designed to have an antenna size as described above. However, no consideration is given to cumulative damage caused by the plurality of antennas to the gate insulating film, and excessive damage to the gate insulating film occurs.
For example, Japanese Patent Laid-open Publication No. 11-186394 discloses a method in which the lengths of wiring connected to a gate electrode are summed, and if the result exceeds a permissible value, certain measures are taken. When the method is applied to conductive members with a multilayered structure, it is contemplated that an antenna size is detected in each of the layers of the conductive members with a multilayered structure and the derived antenna sizes are summed.
In the case of the conductive members with a multilayered structure, however, since the respective layers are not subjected to the same processing, the degrees of damage to a gate electrode may vary even with the same antenna sizes. In addition, the conductive members with a multilayered structure are configured, for example, to connect wiring patterns formed on the surfaces of the respective layers through contact vias, in which the permissible antenna ratios of the wiring patterns are different from those of the contact vias.
Thus, it is actually difficult to form actual conductive members with a multilayered structure with optimal antenna sizes when cumulative antenna size &Sgr;Mi of the conductive members is set as described above to satisfy the following relationship with respect to area Sj of the gate insulating film and maximum permissible antenna ratio R
0
:
Mi≦R
0×
Sj
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and an apparatus of circuit design capable of designing conductive members with a multilayered structure connected to a gate insulating film of a transistor element to have antenna sizes of proper values in design of an integrated circuit device including the conductive members.
In a circuit design method of the present invention, for designing an integrated circuit device including conductive members with a multilayered structure connected to a gate insulating film of a transistor element, individual damage is calculated first for each of a plurality of antenna units of the conductive members with a multilayered structure. The integrated circuit device is designed such that a total amount of the separately calculated individual damage is less than a predetermined permissible amount. Therefore, even when the plurality of antenna units of the conductive members with a multilayered structure have different degrees of damage or antenna ratios from one another, the total amount of damage to the gate insulating film can be accurately calculated.
In another circuit design method of the present invention, from antenna size Mi of each of n antenna units of the conductive members and actual area Sj of the gate insulating film, antenna ratio Ri is calculated for each of the n antenna units of the conductive members as Ri=Mi/Sj. In addition, from maximum permissible antenna ratio Rmi of each of the n antenna units of the conductive members with respect to actual area Sj of the gate insulating film, individual damage Di is calculated as Di=f(Ri/Rmi) for each of the n antenna units of the conductive members with respect to actual area Sj of the gate insulating film. From the calculation results, damage total amount &Sgr;D acting on the gate insulating film is calculated as &Sgr;D=D
1
+D
2
+ . . . +Dn. The integrated circuit device is designed such that damage total amount &Sgr;D is less than 1.
Therefore, an integrated circuit device designed with the circuit design method of the present invention is designed to achieve proper antenna sizes in a plurality of antenna units of conductive members with a multilayered structure connected to a gate insulating film of a transistor element. Thus, even when plasma processing in the manufacturing process results in electrical charges flowing into the plurality of antenna units of the conductive members with a multilayered structure, damage accumulated on the gate insulating film does not become critical.
In an embodiment of the present invention, individual damage Di of each of n an
Callahan Timothy P.
Luu An T.
NEC Corporation
Young & Thompson
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