Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-05
2003-09-23
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S529000, C365S103000
Reexamination Certificate
active
06624485
ABSTRACT:
BACKGROUND
This invention relates to low-cost, mask-programmed read only memories.
In a conventional manufacturing process for semiconductor integrated circuits, finished wafer cost is almost completely independent of the number of individual die printed on the wafer. Thus die cost is equal to wafer cost divided by the number of die on the wafer. The larger the number of die printed on the wafer, the lower the cost per die. IC manufacturers therefore have a strong incentive to decrease diesize; it allows them to build more die on a (fixed cost) wafer, thereby lowering the cost per die.
Smaller die are desirable for a second reason: the manufacturing yield (the number of good die divided by the total number of die) goes down as the diesize goes up. A smaller diesize gives both a higher yield and a larger number of die sites on the wafer.
Designers of IC's for cost-sensitive applications are well aware of the benefits of small diesize, and they strive to reduce diesize wherever possible. An emerging trend in low-cost IC memory design is to build several “levels” or “planes” of memory cells vertically stacked above one another in a 3-dimensional array. A memory chip having N planes of memory cells in a 3D array can be built in approximately (1/Nth) of the die area of a conventional memory chip having 1 plane of cells in a 2D array. Examples of this technique include Roesner U.S. Pat. No. 4,442,507, Zhang U.S. Pat. No. 5,835,396, Holmberg U.S. Pat. No. 4,499,557, Ovshinsky U.S. Pat. No. 4,646,266, and Johnson U.S. Pat. No. 6,185,122.
Memories which may be written by the end-user are called “field programmable” memories and offer great flexibility, as compared to memories which are written during the manufacturing process and whose contents are not alterable by the end-user (“mask ROMs”). However, the flexibility afforded by field programmable memories also has a cost. Field programmable memories must include additional circuitry that is not needed in mask ROMs, and these extra circuits consume chip area and increase diesize. Mask ROMs do not need data-in circuits, write circuits, or VPP chargepumps; field programmable memories do. Thus mask ROMs can be made with smaller diesize (hence lower cost) than field programmable memories.
For very low cost applications, mask ROMs are preferred because their diesize is smaller (due to the lack of data-in circuits, VPP pumps, write circuits, etc.) Additionally, 3-dimensional memories are preferred because their diesize is approximately 1/Nth as large as 2-dimensional memories. Therefore what is desired is a 3-dimensional memory that is a mask ROM.
Zhang U.S. Pat. No. 5,835,396 discusses embodiments of 3D mask ROMs. However, the semiconductor structures of the Zhang patent require approximately five masking steps per plane of cells: (1) wordline; (2) wordline contact to substrate; (3) bitline; (4) bitline contact to substrate; (5) memory cell programmation via. A memory chip containing N planes of such cells would thus include 5N masking steps to build the array.
Finished wafer cost rises with the number of masking steps used in fabrication, and it is therefore desirable to reduce the number of masking steps required to fabricate a 3D, mask-programmed memory array.
SUMMARY
The preferred embodiments described below are 3D, mask-programmed memory arrays having multiple layers of wordlines and multiple layers of bitlines arranged to cross the wordlines. Except for wordlines positioned at the top or the bottom of the array, each wordline connects (1) to multiple underlying bitlines via respective underlying memory cells and (2) to multiple overlying bitlines via respective overlying memory cells. Similarly, except for bitlines positioned at the top or the bottom of the array, each bitline connects (1) to multiple underlying wordlines via respective underlying memory cells and (2) to multiple overlying wordlines via respective overlying memory cells. Each memory cell includes a respective portion of a respective mask-programmed insulating layer, and the logical state of each memory cell is determined by the conductivity of the respective insulating layer portion. Each memory cell also includes two respective diode components arranged to prevent addressing ambiguity.
The preceding paragraphs have been provided by way of general introduction, and they are not intended to narrow the scope of the following claims.
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Brinks Hofer Gilson & Lione
Elms Richard
Matrix Semiconductor Inc.
Smith Brad
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