Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-10-08
2003-07-01
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185050, C365S185180
Reexamination Certificate
active
06587373
ABSTRACT:
BACKGROUND
This invention relates generally to memory devices and particularly to memory devices with a multilevel cell architecture.
A multilevel cell memory is comprised of multilevel cells, each of which is able to store multiple charge states or levels. Each of the charge states is associated with a memory element bit pattern.
A flash EEPROM memory cell, as well as other types of memory cells, is configurable to store multiple threshold levels (V
t
). In a memory cell capable of storing two bits per cell, for example, four threshold levels (V
t
) are used. Consequently, two bits are designated for each threshold level.
In one embodiment, the multilevel cell may store four charge states. Level 3 maintains a higher charge than level 2, level 2 maintains a higher charge than level 1, and level 1 maintains a higher charge than level 0. A reference voltage may separate the various charge states. For example, a first voltage reference may separate level 3 and level 2, a second voltage reference may separate level 2 from level 1, and a third reference voltage may separate level 1 from level 0.
A multilevel cell memory is able to store more than one bit of data based upon the number of charge states. For example, a multilevel cell memory that can store four charge states can store two bits of data, a multilevel cell memory that can store eight charge states can store three bits of data, and a multilevel cell that can store sixteen charge states can store four bits of data. For each of the n-bit multilevel cell memories, various memory element bit patterns can be associated with each of the different charge states.
The number of charge states storable in a multilevel cell, however, is not limited to powers of two. For example, a multilevel cell with three charge states stores 1.5 bits of data. When this multilevel cell is combined with additional decoding logic and coupled to a second similar multilevel cell, three bits of data are provided as the output of the two-cell combination. Various other multi-cell combinations are also possible.
The retrieval of information from multilevel cell memories is currently slower than the retrieval from single-bit cell memories because the sensing time of multilevel cell memories is greater. This is primarily because sensing more than one bit takes more time than sensing one bit.
Generally, with conventional multilevel cell designs, a word may consist of a plurality of bits. A first set of two bits of the word may be stored in the same cell(in a 2 bit multilevel cell example) and then the next set of two bits may be stored in the same cell and so on to store the entire word. Then, to access to word, after decoding, both the first and second bits of the cell are sensed. Only when both bits have been sensed is the output accessible. In effect, then, the output must wait for both the first and the second bits to be sensed.
Thus, there is a need for a way to decrease access times for multilevel cell memories.
REFERENCES:
patent: 5574879 (1996-11-01), Wells et al.
patent: 5754566 (1998-05-01), Christopherson et al.
patent: 5937423 (1999-08-01), Robinson
patent: 6023781 (2000-02-01), Hazama
patent: 6195284 (2001-02-01), Egawa
patent: 6424566 (2002-07-01), Parker
Dinh Son T.
Intel Corporation
Trop Pruner & Hu P.C.
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