Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-23
2003-08-05
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000, C257S350000, C438S149000, C438S219000, C438S479000
Reexamination Certificate
active
06603174
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having an SOI (Silicon On Insulator) structure, and a manufacturing method thereof.
2. Background of the Invention
FIGS. 37 through 47
are longitudinal cross-sectional views of a semiconductor device having a conventional SOI structure, showing successive stages of a manufacturing process. Using the drawings, we will describe the structure of a conventional semiconductor device at each step.
First prepared is an SOI substrate
130
A shown in
FIG. 37
, formed for example by an SIMOX (Separation by implanted Oxygen) method. As shown, the SOI substrate
130
A comprises a buried oxide film
102
and an SOI layer of single crystalline silicon
103
A formed sequentially on one surface of the silicon substrate
101
. The SOI substrate
130
A may be formed by other methods such as wafer bonding, as long as having such a structure.
Next, as shown in
FIG. 38
, the surface of the SOI layer
103
A in the SOI substrate
130
A is oxidized to form a silicon oxide film
104
A having a thickness of about 100 Å to 300 Å. And a silicon nitride film
105
A having a thickness of about 2000 Å is deposited thereon. The silicon oxide film
104
A can be formed by other methods such as CVD using TEOS (Tetra Ethyl Ortho Silicate). The silicon oxide film
104
A and the silicon nitride film
105
A are then patterned by photolithography and dry etching to form a silicon oxide film (hereinafter referred to also as an “underlying oxide film”)
104
and a silicon nitride film
105
as shown in
FIG. 39. A
region where the underlying oxide film
104
and the silicon nitride film
105
are formed is referred to as an active region
151
, while a region except the active region
151
is referred to as an isolation region
152
.
After that, the SOI layer
103
A is anisotropically etched with the silicon nitride film
105
used as a mask, to form an SOI layer
103
as shown in FIG.
40
. The silicon substrate
101
, the buried oxide film
102
, and the SOI layer
103
after this etching are generically referred to as an “SOI substrate
130
”.
Then, as shown in
FIG. 41
, a silicon oxide film
108
A having a thickness at least larger than a difference in level between the active region
151
and the isolation region
152
(about 5000 Å, for example) is deposited to cover the overall exposed surface of the SOI substrate
130
.
The silicon oxide film
108
A is then polished for planarization by a CMP (Chemical Mechanical Polishing) method, as shown in
FIG. 42
, to the extent that the silicon nitride film
105
is exposed. After the polishing, part of the silicon oxide film
108
A remains on the isolation region
152
of the buried oxide film
102
, as a silicon oxide film
108
B.
Next, the silicon nitride film
105
is removed by phosphoric acid of about 160° C. (see FIG.
43
).
Then, after channel implantation through the underlying oxide film
104
, the film
104
is removed by hydrofluoric acid. At the same time, the silicon oxide film
108
B is etched to a predetermined depth to form a silicon oxide film
108
shown in FIG.
44
.
After that, as shown in
FIG. 45
, a silicon oxide film
109
A having a thickness of about 70 Å is formed to cover the exposed surface
103
S (cf.
FIG. 44
) of the SOI layer
103
. Subsequently, an electrode layer
110
A having a thickness of about 2000 Å is formed as shown in FIG.
46
. The silicon oxide film
109
A and the electrode layer
110
A are then patterned by photolithography and dry etching to form a gate oxide film
109
and a gate electrode
110
shown in FIG.
47
. Then, semiconductor regions
120
A and
120
B each forming a source or drain region are formed by implanting an impurity into a predetermined region. After an interlayer oxide film
111
is formed across the surface of the SOI substrate
130
, contact holes CAP and CBP are formed in the surface of the interlayer oxide film
111
so as to reach the source or drain regions
120
A and
120
B, respectively, as shown in FIG.
47
. The contact holes CAP and CBP are filled with a wiring material, such as aluminum, to form wires
112
A and
112
B, respectively. In this manner, the SOI/MOSFET shown in
FIG. 47
is obtained.
According to the manufacturing process described above, when the underlying oxide film
104
in the semiconductor device shown in
FIG. 43
is removed by etching using hydrofluoric acid, the silicon oxide film
108
B is etched at the same time. Since the etch rate of the silicon oxide film
108
B is larger than that of the underlying oxide film
104
formed by thermal oxidation, the silicon oxide film
108
B will be overetched in the vicinity of the Si/SiO
2
interface between the SOI layer
103
and the silicon oxide film
108
B. This makes that portion of the silicon oxide film
108
B smaller in height (thickness) than the SOI layer
103
. Such a portion will be referred to as a depression
200
.
FIG. 48
is a longitudinal cross-sectional view taken along a line X—X in
FIG. 47
, when viewed from the direction indicated by the arrow.
FIG. 49
is an enlarged cross-sectional view showing a vicinity of the depression
200
in
FIG. 48
(a region AP indicated by dashed lines).
In the semiconductor device with the depression
200
shown in
FIG. 44
, when the silicon oxide film
109
A and the electrode layer
110
A are sequentially formed on the surface
103
S of the SOI layer
103
, their shapes will be affected by the depression
200
as shown in FIG.
46
. Accordingly, the depression
200
will affect the shapes of the gate oxide film
109
and the gate electrode
110
which are obtained by patterning the silicon oxide film
109
A and the conductive material
110
A, as shown in FIG.
48
.
A conventional MOSFET
140
with the depression
200
, as shown in
FIG. 49
, comprises not only a real MOSFET
140
S but also a parasitic MOSFET
140
T formed at the end portion of the SOI layer
103
. More specifically, the real MOSFET
140
S has a gate electrode structure comprising a gate oxide film
109
S and a gate electrode
110
S formed on the surface
103
S of the SOI layer
103
, and the parasitic MOSFET
140
T has a gate electrode structure comprising a gate oxide film
109
T and a gate electrode
110
T formed on the side surface
103
T of the SOI layer
103
.
Since an electric field is applied both to the real MOSFET
140
S and to the parasitic MOSFET
140
T, a large electric field is applied to the end portion of the SOI layer
103
in the conventional MOSFET
140
. This causes, with lower voltage than the threshold value of the real MOSFET
140
S, a flow of drain current at the end portion of the conventional MOSFET
140
(problem (1)). That is, there has been a problem that the conventional MOSFET
140
with the depression
200
cannot ensure designed device characteristics due to the parasitic MOSFET
140
T.
Further, a strong electric field to be applied to the end portion of the conventional MOSFET
140
is likely to cause degradation in insulation of the gate oxide film
109
, namely, the gate oxide films
109
T and
109
S, in the vicinity of the end portion (problem (2)). This may cause improper operation of the conventional MOSFET
140
even with relatively low gate voltage.
Further, in the conventional MOSFET
140
as shown in
FIG. 49
, the SOI layer
103
and the silicon oxide film
108
under the bottom of the depression form an Si/SiO
2
interface. Since the silicon oxide film
108
is a film formed by deposition such as CVD, the Si/SiO
2
interface has relatively a lot of interface states. Thus, a large difference in potential between the bottom of the depression
200
and the SOI layer
103
is likely to cause degradation in insulation of the silicon oxide film
108
at the Si/SiO
2
interface (problem (3)). Such degradation in insulation at the interface equals degradation in insulation of the parasitic MOSFET
140
T, thereby resu
Hirano Yuuichi
Ipposhi Takashi
Miyamoto Shoichi
Kang Donghee
Thomas Tom
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