Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-24
2003-04-01
Le, Vu A. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S266000, C257S337000, C257S341000
Reexamination Certificate
active
06541819
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuits and, more specifically, to a semiconductor device having a non-power enhanced metal oxide semiconductor (non-PEMOS) devices and power enhanced metal oxide semiconductor (PEMOS) devices, and a method of manufacture therefor.
BACKGROUND OF THE INVENTION
Complementary metal oxide semiconductor (CMOS) devices are commonly used and well known in the microelectronics industry. Such CMOS devices are generally used as logic devices, memory devices, or other similar devices. In addition to CMOS devices, laterally diffused metal oxide semiconductor (LDMOS) devices are also commonly used and well known in the microelectronics industry. LDMOS devices are generally used in an area of microelectronics called power management. Power management refers to a collection of circuits used to control the delivery of power to a particular device, such as a microprocessor, optical device, micro-electro-mechanical system (MEMS) device or another device.
There is currently a desire in the microelectronics industry to integrate conventional CMOS devices and LDMOS devices on a single semiconductor substrate. An example of a conventional integrated circuit
100
having both CMOS devices
120
and LDMOS devices
150
on a single semiconductor substrate
110
, is illustrated in FIG.
1
. It should be noted that due to the stringent requirements in constructing the CMOS devices
120
and the LDMOS devices
150
, manufacturing the integrated circuit
100
may be complicated. For instance, the CMOS devices
120
and LDMOS devices
150
have different requirements associated with the dopant depths and concentrations in the respective CMOS wells
130
and LDMOS wells
160
. There are also differences between CMOS and LDMOS heavily doped source/drain regions
135
,
165
, and the CMOS and LDMOS lightly doped source/drain regions
140
,
170
of the corresponding CMOS and LDMOS devices
120
,
150
, which further exacerbate the difficulties in constructing the integrated circuit
100
.
In view of the manufacturing complications associated with integrating both the CMOS devices and LDMOS devices
120
,
150
, on a single semiconductor substrate, the microelectronics industry currently manufactures the devices using completely separate processing steps. For example, the CMOS devices
120
are generally formed on the semiconductor substrate
110
and subsequently masked off, followed by the formation of the LDMOS devices
150
, or vice versa if desired. Using completely separate manufacturing steps to produce the CMOS devices
120
and LDMOS devices
150
substantially achieves the end result, however, at a sacrifice. It currently requires up to an additional 15 steps to produce the LDMOS devices
150
over the number of steps to manufacture the CMOS devices
120
. As a result, manufacturing time and cost increases, which one skilled in the art generally knows is undesirable.
Accordingly, what is needed in the art is a semiconductor device including devices employable for power management and other devices (e.g., CMOS devices) on the same semiconductor substrate, and a method of manufacture therefor, that does not experience difficulties associated with the prior art, such as the high manufacturing time and costs associated with the prior art devices.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device. The semiconductor device includes a non-power enhanced metal oxide semiconductor (non-PEMOS) device, such as a complementary metal oxide semiconductor (CMOS) device, having first source/drain regions located in a semiconductor substrate, wherein the first source/drain regions include a first dopant profile. The semiconductor device further includes a power enhanced metal oxide semiconductor (PEMOS) device, such as a laterally diffused metal oxide semiconductor (LDMOS) device, located adjacent the non-PEMOS device and having second source/drain regions located in the semiconductor substrate, wherein the second source/drain regions include the first dopant profile.
Provided in another aspect of the invention is a method of manufacturing a semiconductor device. The method includes forming a non-PEMOS device over a semiconductor substrate using a predetermined number of steps, and simultaneously creating at least a portion of a PEMOS device over the semiconductor substrate using at least one of the predetermined number of steps.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5726477 (1998-03-01), Williams
patent: 5852314 (1998-12-01), Depetro
patent: 5917222 (1999-06-01), Smayling
patent: 6258644 (2001-07-01), Rodder et al.
patent: 6277682 (2001-08-01), Misium
US 6,104,076, 8/2000, Nakayama (withdrawn)
Lotfi Ashraf W.
Tan Jian
Agere Systems Inc.
Le Vu A.
Menz Doug
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