Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-13
2003-07-01
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000
Reexamination Certificate
active
06586809
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and in particular, relates to measures for improving the reliability of the semiconductor device.
In recent years, with the scaledown and operation speedup of LSIs, reduction in the sizes of individual parts of a MISFET of an LSI according to scaling rules have been requested. In particular, it has become increasingly necessary to reduce the margin between the gate electrode and the contacts to the active regions as the source/drain of the MISFET. In general, in a self-alignment contact (SAC) structure in which source/drain contacts are allowed to overlap a gate electrode and sidewalls, it is necessary to prevent short-circuiting between the contacts and the gate electrode and short-circuiting between the contacts and regions of the semiconductor substrate right under the sidewalls. For this purpose, a gate-top protection film and the sidewalls of the gate electrode are made of a silicon nitride film because the silicon nitride film has a high dry-etching selective ratio with respect to an oxide film constituting an interlayer insulating film.
FIGS. 8A
to
8
C are cross-sectional views showing a conventional fabrication process of a p-channel MISFET of the SAC structure having a poly-metal gate electrode. In general, an n-channel MISFET is also formed in another region although illustration of the fabrication process thereof is omitted in
FIGS. 8A
to
8
C.
Referring to
FIG. 8A
, a silicon oxide-nitride film serving as a gate insulating film is formed on the principal plane of a Si substrate
101
. A polysilicon film is then deposited on the silicon oxide-nitride film by LPCVD. During this deposition, the polysilicon film is also deposited on the back surface of the Si substrate as a back polysilicon film
120
. Boron ions (B
+
) as p-type impurity ions are implanted in a portion of the polysilicon film on the principal plane side located in a p-channel MISFET formation region under the conditions of an accelerating energy of 5 keV and a dose of 3×10
15
cm
−2
. Note that in general n-type impurity ions are implanted in an n-channel MISFET formation region. A metal film having a thickness of 50 nm is then deposited by sputtering, and subsequently a silicon nitride film having a thickness of 100 nm is deposited on the metal film. During this deposition, the silicon nitride film is also deposited on the surface of the back polysilicon film
120
on the back side of the Si substrate
101
, as a back silicon nitride film
121
. Thereafter, the silicon nitride film, the metal film, the polysilicon film and the silicon oxide-nitride film formed on the principal plane side of the Si substrate
101
are patterned by photolithography and dry etching, to form a gate electrode portion
113
essentially composed of a gate insulating film
102
, a lower gate electrode
103
, an upper gate electrode
104
and a gate-top protection film
105
on the Si substrate
101
.
Thereafter, a resist mask is formed covering the n-channel MISFET formation region while leaving the p-channel MISFET formation region open. In this state, boron fluoride ions (BF
2
+
) as p-type impurity ions are implanted in the Si substrate
101
using the gate electrode portion
113
as a mask under the conditions of an accelerating energy of 10 kev and a dose of 3.0×10
14
cm
−2
, to form p-type LDD layers
106
.
Referring to
FIG. 8B
, after removal of the resist mask, a silicon nitride film is deposited on the resultant substrate to a thickness of 80 nm by LPCVD. The silicon nitride film is then etched back to form nitride film sidewalls
107
on the sides of the gate electrode portion
113
. During this etch-back, a back silicon nitride film
122
formed during the deposition of the silicon nitride film for the sidewalls remains unremoved on the back silicon nitride film
121
on the back side of the Si substrate
101
. Thereafter, a resist mask is formed again covering the n-channel MISFET formation region while leaving the p-channel MISFET formation region open. In this state, boron fluoride ions (BF
2
+
) as p-type impurity ions are implanted in the Si substrate
101
using the gate electrode portion
113
and the nitride film sidewalls
107
as a mask under the conditions of an accelerating energy of 50 keV and a dose of 5.0×10
15
cm
−2
, to form p-type source/drain regions
108
.
The impurities implanted in the LDD regions
106
and the source/drain regions
108
are then activated by rapid thermal annealing (RTA) at 1000° C. for 10 seconds.
Subsequently, a Co film having a thickness of 8 nm is deposited on the resultant substrate and subjected to thermal treatment at 500° C. for 60 seconds to allow Si to react with Co to form cobalt silicide films
109
on the source/drain regions
108
. Unreacted part of the Co film is then removed by etching.
Referring to
FIG. 5C
, an interlayer insulating film
110
made of a BPSG film having a thickness of 800 nm is deposited on the resultant substrate and smoothed by chemical mechanical polishing (CMP). Contact holes are then formed through the interlayer insulating film
110
to reach the cobalt silicide films
109
on the source/drain regions
108
by dry etching using a resist mask. The contact holes are filled with tungsten and the like to form source/drain contacts
111
. During this formation, no margin is set for alignment between the photomask used for the gate electrode patterning and the photomask used for the contact hole formation (self-alignment). Therefore, the size of the MISFET formation region can be reduced.
Thereafter, a metal film such as an aluminum alloy film is deposited on the interlayer insulating film
110
and then patterned to form metal interconnections
112
on the interlayer insulating film
110
to be connected with the source/drain contacts
111
.
During the formation of interconnections, heat treatment in a hydrogen atmosphere (hydrogen sintering) is performed at 400° C. for 30 minutes, for example, for recovery from a fixed level induced at the interface between the Si substrate
101
and the gate insulating film
102
and a damage layer in the Si substrate
101
.
The MIS transistor fabricated in the conventional process described above has the following problems.
In a process step shown in
FIG. 8A
, the lower gate electrode
103
and the back surface of the Si substrate
101
are subjected to the high-temperature heat treatment in the state that they are covered with the gate-top protection film
105
made of a nitride film and the back silicon nitride film
121
. This results in that they receive intense stress from the silicon nitride films. In addition, during the formation of the silicon nitride film by LPCVD, hydrogen enters the silicon nitride film. Such hydrogen fails to be diffused to the outside by being interfered by the silicon nitride film itself and remains inside the gate electrode. With the existence of hydrogen in the gate electrode and also the existence of the stress as described above, intrusion of boron in the gate electrode into the gate insulating film
102
and the Si substrate
101
is facilitated during the activation of the impurities implanted in the source/drain regions
108
and the like. As a result, the flat band voltage of the MIS capacitor may decrease, and this may possibly increases the variation in the threshold voltage of the transistor.
The lower gate electrode
103
and the back surface of the Si substrate
101
are covered with the gate-top protection film
105
made of a nitride film and the back silicon nitride film
121
as described above. This causes another problem of insufficient supply of hydrogen to the gate insulating film
102
and the Si substrate
101
during the hydrogen sintering. As a result, recovery from a fixed level induced at the interface between the Si substrate
101
and the gate insulating film
102
and a damage layer in the Si substrate
101
is insufficient. This may possibly det
Prenty Mark V.
Studebaker Donald R.
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