Semiconductor structure having multiple levels of self-aligned i

Details Semiconductor structure having multiple levels of self-aligned i Semiconductor structure having multiple levels of self-aligned i

1996-02-07

1997-09-02

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438672, H01L 2144

Patent

active

056631014

ABSTRACT:
An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.
An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.

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IBM Technical Disclosure Bulletin vol. 31 No. 4 Sep. 1988 pp. 400-401.

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