Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-15
2003-09-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06627951
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
BACKGROUND OF THE INVENTION
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use diffusion to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage circuits for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
One problem frequently experienced with trench DMOS transistors is known as punch-through. Punch-through, which arises when the transistor channel is depleted, typically takes the form of a non-destructive leakage current prior to avalanche breakdown. It has been found that punch-through is particularly deleterious at higher transistor cell densities, notably at densities greater than about 18M/in
3
. While punch-through can have many causes, one significant cause of punch-through occurs during the formation of the trench gate. In particular, after the trench has been etched, a sacrificial oxidation step is performed to smooth the trench sidewalls, which is then followed by deposition of the thin oxide layer. During the sacrificial oxidation and oxide deposition steps, dopant material leaches out of the adjacent channel (the so-called p-body) because dopant material (typically boron) segregates from the silicon into the oxide during the sacrificial oxidation step, which is performed at high temperatures. This problem is exacerbated at higher cell densities, because the relative width of the channel decreases with respect to the surface area encompassed by the trench.
Punch-through is also aggravated when polysilicon is deposited to fill the trench because the dopant (typically phosphorous) employed in the polysilicon can penetrate through the gate into the p-body, which effectively reduces the concentration of carriers in the channel. This problem becomes more severe as the thickness of the gate oxide layer lining the trench is reduced.
U.S. Pat. No. 5,072,266 discloses a conventional sequence of processing steps that are employed to fabricate a trench DMOS transistor. In this process, the p-body channel and the source regions are formed before the trench. As previously mentioned, however, during the formation of the trench, dopant materials can leach out of the p-body, increasing punch-through. As a result, the depth of the trench and the p-body must be increased to compensate for the increase in punch-through. Moreover, the source regions may also be adversely effected during the formation of the trench because of silicon defects produced in the source regions during the oxidation steps used in forming the trench gate.
U.S. Pat. No. 5,468,982 attempts to reduce punch-through by forming the p-body after the trench gate has been etched and filled. This approach is not entirely satisfactory, however, since the formation of the p-body requires a diffusion step that involves high temperatures (typically 1100-1150° C.). These high temperatures allow the dopant material in the polysilicon that fills the trench to penetrate through the gate oxide at a greater rate, thus contributing to an increase in punch-through.
Another problem with existing trench DMOS is switching speed. There is a significant emphasis in the industry toward producing discrete DMOS circuits with higher cell densities. However, as cell density is increased, trench widths must be shrunk in order to achieve design requirements, and the narrower trench widths result in higher gate resistance. Consequently, switching speed becomes an important consideration.
Polycide, such as WSi
2
and TiSi
2
, and refractory metals and alloys such as W and TiW, have been used in advanced logic processes to increase the switching speeds of devices and IC circuits. However, it is still not common to use polycide or refractory metal techniques in trench DMOS, due in part to the fact that the higher switching speeds which are theoretically achievable with these materials has not been realized. The reason for this can be understood by considering a typical prior art trench DMOS equipped with a double-layer gate. The gate is produced by selective CVD tungsten. In trench DMOS of this type, the P-body and source are formed before the trench gate is formed. Transistors of this type have at least two drawbacks. Firstly, silicon defects are easily formed in the source region during subsequent oxidation processes, such as sacrificial and gate oxidations. Since the source region is typically heavily doped with arsenic, this results in poor gate oxide integrity in this region. Secondly, transistors of this type typically have a deeper source junction depth due to the subsequent oxidation processes, which requires a deeper P-body and trench in order to prevent punch-through. Consequently, the device has higher parasitic capacitance, which reduces the benefit gained from the tungsten/poly gate.
There thus remains a need in the art for a trench DMOS, and a method for making the same, in which the trench DMOS has a low gate resistance and low capacitance, thereby reducing the distributed RC gate propagation delay and improving switching speed for high frequency applications. There is also a need in the art for a method for making a trench DMOS that reduces or eliminates punch-through. These and other needs are met by the present invention, as hereinafter disclosed.
SUMMARY OF THE INVENTION
The present invention relates to methods for creating trench DMOS, and to the trench DMOS so made. In accordance with the invention, polycide and refractory techniques are used to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, reduced punch-through, and improved switching speeds for high frequency applications.
In one aspect, the present invention relates to a method for making trench DMOS, and to the trench DMOS so made. In accordance with the method, the source, which may be an n+ source, is formed after gate oxidation. This allows the junction depth to be controlled within a very shallow range (e.g., 0.2 to 0.5 &mgr;m), which reduces parasitic capacitance by allowing the use of a shallower P-body and shallower trench depth without increasing the risk of drain/source punch-through. The formation of the source after gate oxidation is also advantageous in that it provides for improved gate oxide integrity, since it eliminates silicon defects in the source region (which is typically heavily doped with arsenic) that would otherwise result from the oxidation processes. Moreover, this methodology results in less stress or void formation between the polysilicon and polycide or refractory metal, since the device is not exposed to any high temperature processes after CVD polycide or refractory metal deposition.
In another aspect, the present invention relates to a trench
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