Decoder for reducing test time for detecting defective...

Details Decoder for reducing test time for detecting defective... Decoder for reducing test time for detecting defective...

Filed on

2001-07-10

Date issued

2003-05-27

Examiner

Tokar, Michael (Department: 2819)

Patent Class

Coded data generation or conversion

SubClass

Converter calibration or testing

Other Related Categories

C341S118000, C341S144000, C365S154000, C365S189050, C365S201000, C365S226000, C365S230010

Type

Reexamination Certificate

Status

active

Patent number

06570515

Description

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to optimization of a test, and more particularly, to a decoder for reducing a test time for detecting defective switches in a digital-to-analog converter.
2. Description of the Related Art
A digital-to-analog converter (DA converter) is a device for converting a discrete digital signal used in contemporary electronic systems to a continuous analog signal which a human can perceive. The DA converter essentially includes a plurality of direct current voltage sources having generally different voltage levels, and a decoder portion having a plurality of switches for switching these voltage sources.
FIG. 1
illustrates a conventional decoder using NMOS transistors as switches.
Referring to
FIG. 1
, the conventional decoder includes eight direct current voltage sources (VL
1
through VL
8
) having different voltage levels, a plurality of NMOS transistors (MN
1
through MN
24
) which are connected to the eight direct current voltage sources (VL
1
through VL
8
) in series in groups of three and used as switches, three digital signals (D
0
through D
2
) for controlling the plurality of NMOS transistors (MN
1
through MN
24
), and three inverters
11
,
12
,
13
for inverting the 3 digital signals, respectively.
When the three digital signals (D
0
through D
2
) are all logic high, the three NMOS transistors (MN
1
through MN
3
) turn on, and the direct current voltage source (VL
1
) is transmitted to an output terminal (VLOUT). When the three digital signals (D
0
through D
2
) are all logic low, three NMOS transistors (MN
22
through MN
24
) turn on, and the direct current voltage source (VL
8
) is transmitted to the output terminal (VLOUT).
FIG. 2
illustrates a conventional decoder using PMOS transistors as switches. Referring to
FIG. 2
, the conventional decoder includes eight direct current voltage sources (VH
1
through VH
8
) having different voltage levels, a plurality of PMOS transistors (MP
1
through MP
24
) which are connected to the eight direct current voltage sources (VH
1
through VH
8
) in series in groups of three, and used as switches, three digital signals (D
0
through D
2
) for controlling the plurality of PMOS transistors, and three inverters (
21
through
23
) for inverting the three digital signals (D
0
through D
2
).
When the three digital signals (D
0
through D
2
) are all logic low, three PMOS transistors (MP
1
through MN
3
) turn on, and the direct current voltage source (VH
1
) is transmitted to an output terminal (VHOUT). When the three digital signals (D
0
through D
2
) are all logic high, three PMOS transistors (MP
22
through MP
24
) turn on, and the direct current voltage source (VH
8
) is transmitted to the output terminal (VHOUT).
Referring to
FIGS. 1 and 2
, one of the eight direct current voltage sources is transmitted to the output terminal (VLOUT) depending on a logic state of the three digital signals (D
0
through D
2
), and a total of three digital signals (D
0
through D
2
) and 24 switches (MN
1
through MN
24
or MP
1
through MP
24
) are required for selecting and outputting eight analog voltage levels. If there are defects in the switches, the decoder malfunctions.
An NMOS transistor or a PMOS transistor is used as a switch, or a transmission gate combining the NMOS transistor and PMOS transistor is used. The probability of occurrence of a malfunction increases as the number of switches used increases. In order to detect malfunctioning switches, all switches connected to the direct current voltage sources must be tested. A conventional method for testing the switches, in which a switch connected to a direct current voltage source in series is tested one at a time, has many shortcomings in terms of time and economic efficiency.
SUMMARY OF THE INVENTION
To address the above limitations, it is an objective of the present invention to provide a decoder including a test controlling portion which turns on all switches in response to an externally applied test order signal, and detects all defective switches simultaneously by applying a specific pattern.
Accordingly, to achieve the above objective, according to a first preferred embodiment of the present invention, a decoder including a switch controlling portion and a switching portion is provided.
The switch controlling portion receives a plurality of digital input signals having digital information related to an analog output signal and at least one test order signal having data indicating a normal mode of operation or a test mode of operation, outputs as control signals the plurality of digital input signals and inverted signals of the plurality of digital input signals when the test order signal orders a normal mode, and outputs as control signals the plurality of digital input signals and signals having the same phase as the plurality of digital input signals when the test order signal orders a test mode.
The switch portion includes a plurality of switches connected to the same number of direct current voltage source inputs having different voltage levels in series, and switches the plurality of direct current voltage sources as a function of the plurality of control signals of the switch controlling portion.
The switch controlling portion preferably includes a plurality of mode selecting circuits. The plurality of mode selecting circuits output an inverted signal of each of the digital input signals when the test order signal orders a normal mode, and output a signal having the same phase as each of the digital input signals when the test order signal orders a test mode. The plurality of mode selecting circuits include NAND gates, in which one input is connected to one signal of the plurality of digital input signals, and the other input is connected to at least one test order signal. Each of the switches of the switch portion is realized as an NMOS transistor.
To achieve the above objective, according to a second preferred embodiment of the present invention, there is provided a decoder, in which the plurality of switches of the switch portion is realized with PMOS transistors instead of NMOS transistors, and the plurality of mode selecting circuits are replaced with NOR gates having one end connected to one signal of the plurality of digital input signals, and the other end connected to at least one test order signal, instead of NAND gates.


REFERENCES:
patent: 4449420 (1984-05-01), Rialan et al.
patent: 5299161 (1994-03-01), Choi et al.
patent: 5841382 (1998-11-01), Walden et al.
patent: 5870043 (1999-02-01), Hiromi
patent: 6249468 (2001-06-01), Kan et al.

Affiliated with

Also associated with

Rating

Decoder for reducing test time for detecting defective... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoder for reducing test time for detecting defective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder for reducing test time for detecting defective... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3076613